cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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swift.h (3147B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* swift.h: Specific definitions for the _broken_ Swift SRMMU
      3 *          MMU module.
      4 *
      5 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
      6 */
      7
      8#ifndef _SPARC_SWIFT_H
      9#define _SPARC_SWIFT_H
     10
     11/* Swift is so brain damaged, here is the mmu control register. */
     12#define SWIFT_ST       0x00800000   /* SW tablewalk enable */
     13#define SWIFT_WP       0x00400000   /* Watchpoint enable   */
     14
     15/* Branch folding (buggy, disable on production systems!)  */
     16#define SWIFT_BF       0x00200000
     17#define SWIFT_PMC      0x00180000   /* Page mode control   */
     18#define SWIFT_PE       0x00040000   /* Parity enable       */
     19#define SWIFT_PC       0x00020000   /* Parity control      */
     20#define SWIFT_AP       0x00010000   /* Graphics page mode control (TCX/SX) */
     21#define SWIFT_AC       0x00008000   /* Alternate Cacheability (see viking.h) */
     22#define SWIFT_BM       0x00004000   /* Boot mode */
     23#define SWIFT_RC       0x00003c00   /* DRAM refresh control */
     24#define SWIFT_IE       0x00000200   /* Instruction cache enable */
     25#define SWIFT_DE       0x00000100   /* Data cache enable */
     26#define SWIFT_SA       0x00000080   /* Store Allocate */
     27#define SWIFT_NF       0x00000002   /* No fault mode */
     28#define SWIFT_EN       0x00000001   /* MMU enable */
     29
     30/* Bits [13:5] select one of 512 instruction cache tags */
     31static inline void swift_inv_insn_tag(unsigned long addr)
     32{
     33	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
     34			     : /* no outputs */
     35			     : "r" (addr), "i" (ASI_M_TXTC_TAG)
     36			     : "memory");
     37}
     38
     39/* Bits [12:4] select one of 512 data cache tags */
     40static inline void swift_inv_data_tag(unsigned long addr)
     41{
     42	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
     43			     : /* no outputs */
     44			     : "r" (addr), "i" (ASI_M_DATAC_TAG)
     45			     : "memory");
     46}
     47
     48static inline void swift_flush_dcache(void)
     49{
     50	unsigned long addr;
     51
     52	for (addr = 0; addr < 0x2000; addr += 0x10)
     53		swift_inv_data_tag(addr);
     54}
     55
     56static inline void swift_flush_icache(void)
     57{
     58	unsigned long addr;
     59
     60	for (addr = 0; addr < 0x4000; addr += 0x20)
     61		swift_inv_insn_tag(addr);
     62}
     63
     64static inline void swift_idflash_clear(void)
     65{
     66	unsigned long addr;
     67
     68	for (addr = 0; addr < 0x2000; addr += 0x10) {
     69		swift_inv_insn_tag(addr<<1);
     70		swift_inv_data_tag(addr);
     71	}
     72}
     73
     74/* Swift is so broken, it isn't even safe to use the following. */
     75static inline void swift_flush_page(unsigned long page)
     76{
     77	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
     78			     : /* no outputs */
     79			     : "r" (page), "i" (ASI_M_FLUSH_PAGE)
     80			     : "memory");
     81}
     82
     83static inline void swift_flush_segment(unsigned long addr)
     84{
     85	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
     86			     : /* no outputs */
     87			     : "r" (addr), "i" (ASI_M_FLUSH_SEG)
     88			     : "memory");
     89}
     90
     91static inline void swift_flush_region(unsigned long addr)
     92{
     93	__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
     94			     : /* no outputs */
     95			     : "r" (addr), "i" (ASI_M_FLUSH_REGION)
     96			     : "memory");
     97}
     98
     99static inline void swift_flush_context(void)
    100{
    101	__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
    102			     : /* no outputs */
    103			     : "i" (ASI_M_FLUSH_CTX)
    104			     : "memory");
    105}
    106
    107#endif /* !(_SPARC_SWIFT_H) */