cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

tlb_64.h (1056B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _SPARC64_TLB_H
      3#define _SPARC64_TLB_H
      4
      5#include <linux/swap.h>
      6#include <linux/pagemap.h>
      7#include <asm/tlbflush.h>
      8#include <asm/mmu_context.h>
      9
     10#ifdef CONFIG_SMP
     11void smp_flush_tlb_pending(struct mm_struct *,
     12				  unsigned long, unsigned long *);
     13#endif
     14
     15#ifdef CONFIG_SMP
     16void smp_flush_tlb_mm(struct mm_struct *mm);
     17#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
     18#else
     19#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
     20#endif
     21
     22void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
     23void flush_tlb_pending(void);
     24
     25#define tlb_start_vma(tlb, vma) do { } while (0)
     26#define tlb_end_vma(tlb, vma)	do { } while (0)
     27#define tlb_flush(tlb)	flush_tlb_pending()
     28
     29/*
     30 * SPARC64's hardware TLB fill does not use the Linux page-tables
     31 * and therefore we don't need a TLBI when freeing page-table pages.
     32 */
     33
     34#ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE
     35#define tlb_needs_table_invalidate()	(false)
     36#endif
     37
     38#include <asm-generic/tlb.h>
     39
     40#endif /* _SPARC64_TLB_H */