cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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psrcompat.h (2070B)


      1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
      2#ifndef _SPARC64_PSRCOMPAT_H
      3#define _SPARC64_PSRCOMPAT_H
      4
      5#include <asm/pstate.h>
      6
      7/* Old 32-bit PSR fields for the compatibility conversion code. */
      8#define PSR_CWP     0x0000001f         /* current window pointer     */
      9#define PSR_ET      0x00000020         /* enable traps field         */
     10#define PSR_PS      0x00000040         /* previous privilege level   */
     11#define PSR_S       0x00000080         /* current privilege level    */
     12#define PSR_PIL     0x00000f00         /* processor interrupt level  */
     13#define PSR_EF      0x00001000         /* enable floating point      */
     14#define PSR_EC      0x00002000         /* enable co-processor        */
     15#define PSR_SYSCALL 0x00004000         /* inside of a syscall        */
     16#define PSR_LE      0x00008000         /* SuperSparcII little-endian */
     17#define PSR_ICC     0x00f00000         /* integer condition codes    */
     18#define PSR_C       0x00100000         /* carry bit                  */
     19#define PSR_V       0x00200000         /* overflow bit               */
     20#define PSR_Z       0x00400000         /* zero bit                   */
     21#define PSR_N       0x00800000         /* negative bit               */
     22#define PSR_VERS    0x0f000000         /* cpu-version field          */
     23#define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
     24
     25#define PSR_V8PLUS  0xff000000         /* fake impl/ver, meaning a 64bit CPU is present */
     26#define PSR_XCC	    0x000f0000         /* if PSR_V8PLUS, this is %xcc */
     27
     28static inline unsigned int tstate_to_psr(unsigned long tstate)
     29{
     30	return ((tstate & TSTATE_CWP)			|
     31		PSR_S					|
     32		((tstate & TSTATE_ICC) >> 12)		|
     33		((tstate & TSTATE_XCC) >> 20)		|
     34		((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
     35		PSR_V8PLUS);
     36}
     37
     38static inline unsigned long psr_to_tstate_icc(unsigned int psr)
     39{
     40	unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;
     41	if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
     42		tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;
     43	return tstate;
     44}
     45
     46#endif /* !(_SPARC64_PSRCOMPAT_H) */