cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

vmlinux.lds.S (3623B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* ld script for sparc32/sparc64 kernel */
      3
      4#include <asm-generic/vmlinux.lds.h>
      5
      6#include <asm/page.h>
      7#include <asm/thread_info.h>
      8
      9#ifdef CONFIG_SPARC32
     10#define INITIAL_ADDRESS  0x10000 + SIZEOF_HEADERS
     11#define TEXTSTART	0xf0004000
     12
     13#define SMP_CACHE_BYTES_SHIFT 5
     14
     15#else
     16#define SMP_CACHE_BYTES_SHIFT 6
     17#define INITIAL_ADDRESS 0x4000
     18#define TEXTSTART      0x0000000000404000
     19
     20#endif
     21
     22#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
     23
     24#ifdef CONFIG_SPARC32
     25OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
     26OUTPUT_ARCH(sparc)
     27ENTRY(_start)
     28jiffies = jiffies_64 + 4;
     29#else
     30/* sparc64 */
     31OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc")
     32OUTPUT_ARCH(sparc:v9a)
     33ENTRY(_start)
     34jiffies = jiffies_64;
     35#endif
     36
     37#ifdef CONFIG_SPARC64
     38ASSERT((swapper_tsb == 0x0000000000408000), "Error: sparc64 early assembler too large")
     39#endif
     40
     41SECTIONS
     42{
     43#ifdef CONFIG_SPARC64
     44	swapper_pg_dir = 0x0000000000402000;
     45#endif
     46	. = INITIAL_ADDRESS;
     47	.text TEXTSTART :
     48	{
     49		_text = .;
     50		HEAD_TEXT
     51		TEXT_TEXT
     52		SCHED_TEXT
     53		CPUIDLE_TEXT
     54		LOCK_TEXT
     55		KPROBES_TEXT
     56		IRQENTRY_TEXT
     57		SOFTIRQENTRY_TEXT
     58		*(.gnu.warning)
     59	} = 0
     60	_etext = .;
     61
     62	RO_DATA(PAGE_SIZE)
     63
     64	/* Start of data section */
     65	_sdata = .;
     66
     67	.data1 : {
     68		*(.data1)
     69	}
     70	RW_DATA(SMP_CACHE_BYTES, 0, THREAD_SIZE)
     71
     72	/* End of data section */
     73	_edata = .;
     74
     75	.fixup : {
     76		__start___fixup = .;
     77		*(.fixup)
     78		__stop___fixup = .;
     79	}
     80	EXCEPTION_TABLE(16)
     81
     82	. = ALIGN(PAGE_SIZE);
     83	__init_begin = ALIGN(PAGE_SIZE);
     84	INIT_TEXT_SECTION(PAGE_SIZE)
     85	__init_text_end = .;
     86	INIT_DATA_SECTION(16)
     87
     88	. = ALIGN(4);
     89	.tsb_ldquad_phys_patch : {
     90		__tsb_ldquad_phys_patch = .;
     91		*(.tsb_ldquad_phys_patch)
     92		__tsb_ldquad_phys_patch_end = .;
     93	}
     94
     95	.tsb_phys_patch : {
     96		__tsb_phys_patch = .;
     97		*(.tsb_phys_patch)
     98		__tsb_phys_patch_end = .;
     99	}
    100
    101	.cpuid_patch : {
    102		__cpuid_patch = .;
    103		*(.cpuid_patch)
    104		__cpuid_patch_end = .;
    105	}
    106
    107	.sun4v_1insn_patch : {
    108		__sun4v_1insn_patch = .;
    109		*(.sun4v_1insn_patch)
    110		__sun4v_1insn_patch_end = .;
    111	}
    112	.sun4v_2insn_patch : {
    113		__sun4v_2insn_patch = .;
    114		*(.sun4v_2insn_patch)
    115		__sun4v_2insn_patch_end = .;
    116	}
    117	.leon_1insn_patch : {
    118		__leon_1insn_patch = .;
    119		*(.leon_1insn_patch)
    120		__leon_1insn_patch_end = .;
    121	}
    122	.swapper_tsb_phys_patch : {
    123		__swapper_tsb_phys_patch = .;
    124		*(.swapper_tsb_phys_patch)
    125		__swapper_tsb_phys_patch_end = .;
    126	}
    127	.swapper_4m_tsb_phys_patch : {
    128		__swapper_4m_tsb_phys_patch = .;
    129		*(.swapper_4m_tsb_phys_patch)
    130		__swapper_4m_tsb_phys_patch_end = .;
    131	}
    132	.popc_3insn_patch : {
    133		__popc_3insn_patch = .;
    134		*(.popc_3insn_patch)
    135		__popc_3insn_patch_end = .;
    136	}
    137	.popc_6insn_patch : {
    138		__popc_6insn_patch = .;
    139		*(.popc_6insn_patch)
    140		__popc_6insn_patch_end = .;
    141	}
    142	.pause_3insn_patch : {
    143		__pause_3insn_patch = .;
    144		*(.pause_3insn_patch)
    145		__pause_3insn_patch_end = .;
    146	}
    147	.sun_m7_1insn_patch : {
    148		__sun_m7_1insn_patch = .;
    149		*(.sun_m7_1insn_patch)
    150		__sun_m7_1insn_patch_end = .;
    151	}
    152	.sun_m7_2insn_patch : {
    153		__sun_m7_2insn_patch = .;
    154		*(.sun_m7_2insn_patch)
    155		__sun_m7_2insn_patch_end = .;
    156	}
    157	.get_tick_patch : {
    158		__get_tick_patch = .;
    159		*(.get_tick_patch)
    160		__get_tick_patch_end = .;
    161	}
    162	.pud_huge_patch : {
    163		__pud_huge_patch = .;
    164		*(.pud_huge_patch)
    165		__pud_huge_patch_end = .;
    166	}
    167	.fast_win_ctrl_1insn_patch : {
    168		__fast_win_ctrl_1insn_patch = .;
    169		*(.fast_win_ctrl_1insn_patch)
    170		__fast_win_ctrl_1insn_patch_end = .;
    171	}
    172	PERCPU_SECTION(SMP_CACHE_BYTES)
    173
    174	. = ALIGN(PAGE_SIZE);
    175	.exit.text : {
    176		EXIT_TEXT
    177	}
    178
    179	.exit.data : {
    180		EXIT_DATA
    181	}
    182
    183	. = ALIGN(PAGE_SIZE);
    184	__init_end = .;
    185	BSS_SECTION(0, 0, 0)
    186	_end = . ;
    187
    188	STABS_DEBUG
    189	DWARF_DEBUG
    190	ELF_DETAILS
    191
    192	DISCARDS
    193}