cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sfp-util_64.h (4141B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * arch/sparc64/math-emu/sfp-util.h
      4 *
      5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
      6 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
      7 *
      8 */
      9
     10#include <linux/kernel.h>
     11#include <linux/sched.h>
     12#include <linux/types.h>
     13#include <asm/byteorder.h>
     14
     15#define add_ssaaaa(sh, sl, ah, al, bh, bl) 	\
     16  __asm__ ("addcc %4,%5,%1\n\t"			\
     17	   "add %2,%3,%0\n\t"			\
     18  	   "bcs,a,pn %%xcc, 1f\n\t"		\
     19  	   "add %0, 1, %0\n"			\
     20  	   "1:"					\
     21	   : "=r" (sh),				\
     22	     "=&r" (sl)				\
     23	   : "r" ((UDItype)(ah)),		\
     24	     "r" ((UDItype)(bh)),		\
     25	     "r" ((UDItype)(al)),		\
     26	     "r" ((UDItype)(bl))		\
     27	   : "cc")
     28	   
     29#define sub_ddmmss(sh, sl, ah, al, bh, bl) 	\
     30  __asm__ ("subcc %4,%5,%1\n\t"			\
     31  	   "sub %2,%3,%0\n\t"			\
     32  	   "bcs,a,pn %%xcc, 1f\n\t"		\
     33  	   "sub %0, 1, %0\n"			\
     34  	   "1:"					\
     35	   : "=r" (sh),				\
     36	     "=&r" (sl)				\
     37	   : "r" ((UDItype)(ah)),		\
     38	     "r" ((UDItype)(bh)),		\
     39	     "r" ((UDItype)(al)),		\
     40	     "r" ((UDItype)(bl))		\
     41	   : "cc")
     42
     43#define umul_ppmm(wh, wl, u, v)				\
     44  do {							\
     45	  UDItype tmp1, tmp2, tmp3, tmp4;		\
     46	  __asm__ __volatile__ (			\
     47		   "srl %7,0,%3\n\t"			\
     48		   "mulx %3,%6,%1\n\t"			\
     49		   "srlx %6,32,%2\n\t"			\
     50		   "mulx %2,%3,%4\n\t"			\
     51		   "sllx %4,32,%5\n\t"			\
     52		   "srl %6,0,%3\n\t"			\
     53		   "sub %1,%5,%5\n\t"			\
     54		   "srlx %5,32,%5\n\t"			\
     55		   "addcc %4,%5,%4\n\t"			\
     56		   "srlx %7,32,%5\n\t"			\
     57		   "mulx %3,%5,%3\n\t"			\
     58		   "mulx %2,%5,%5\n\t"			\
     59		   "sethi %%hi(0x80000000),%2\n\t"	\
     60		   "addcc %4,%3,%4\n\t"			\
     61		   "srlx %4,32,%4\n\t"			\
     62		   "add %2,%2,%2\n\t"			\
     63		   "movcc %%xcc,%%g0,%2\n\t"		\
     64		   "addcc %5,%4,%5\n\t"			\
     65		   "sllx %3,32,%3\n\t"			\
     66		   "add %1,%3,%1\n\t"			\
     67		   "add %5,%2,%0"			\
     68	   : "=r" (wh),					\
     69	     "=&r" (wl),				\
     70	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
     71	   : "r" ((UDItype)(u)),			\
     72	     "r" ((UDItype)(v))				\
     73	   : "cc");					\
     74  } while (0)
     75  
     76#define udiv_qrnnd(q, r, n1, n0, d) 			\
     77  do {                                                  \
     78    UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m;     \
     79    __d1 = (d >> 32);                                   \
     80    __d0 = (USItype)d;                                  \
     81                                                        \
     82    __r1 = (n1) % __d1;                                 \
     83    __q1 = (n1) / __d1;                                 \
     84    __m = (UWtype) __q1 * __d0;                         \
     85    __r1 = (__r1 << 32) | (n0 >> 32);                   \
     86    if (__r1 < __m)                                     \
     87      {                                                 \
     88        __q1--, __r1 += (d);                            \
     89        if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
     90          if (__r1 < __m)                               \
     91            __q1--, __r1 += (d);                        \
     92      }                                                 \
     93    __r1 -= __m;                                        \
     94                                                        \
     95    __r0 = __r1 % __d1;                                 \
     96    __q0 = __r1 / __d1;                                 \
     97    __m = (UWtype) __q0 * __d0;                         \
     98    __r0 = (__r0 << 32) | ((USItype)n0);                \
     99    if (__r0 < __m)                                     \
    100      {                                                 \
    101        __q0--, __r0 += (d);                            \
    102        if (__r0 >= (d))                                \
    103          if (__r0 < __m)                               \
    104            __q0--, __r0 += (d);                        \
    105      }                                                 \
    106    __r0 -= __m;                                        \
    107                                                        \
    108    (q) = (UWtype) (__q1 << 32)  | __q0;                \
    109    (r) = __r0;                                         \
    110  } while (0)
    111
    112#define UDIV_NEEDS_NORMALIZATION 1  
    113
    114#define abort() \
    115	return 0
    116
    117#ifdef __BIG_ENDIAN
    118#define __BYTE_ORDER __BIG_ENDIAN
    119#else
    120#define __BYTE_ORDER __LITTLE_ENDIAN
    121#endif