cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pm.c (2984B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/* -*- linux-c -*- ------------------------------------------------------- *
      3 *
      4 *   Copyright (C) 1991, 1992 Linus Torvalds
      5 *   Copyright 2007 rPath, Inc. - All Rights Reserved
      6 *
      7 * ----------------------------------------------------------------------- */
      8
      9/*
     10 * Prepare the machine for transition to protected mode.
     11 */
     12
     13#include "boot.h"
     14#include <asm/segment.h>
     15
     16/*
     17 * Invoke the realmode switch hook if present; otherwise
     18 * disable all interrupts.
     19 */
     20static void realmode_switch_hook(void)
     21{
     22	if (boot_params.hdr.realmode_swtch) {
     23		asm volatile("lcallw *%0"
     24			     : : "m" (boot_params.hdr.realmode_swtch)
     25			     : "eax", "ebx", "ecx", "edx");
     26	} else {
     27		asm volatile("cli");
     28		outb(0x80, 0x70); /* Disable NMI */
     29		io_delay();
     30	}
     31}
     32
     33/*
     34 * Disable all interrupts at the legacy PIC.
     35 */
     36static void mask_all_interrupts(void)
     37{
     38	outb(0xff, 0xa1);	/* Mask all interrupts on the secondary PIC */
     39	io_delay();
     40	outb(0xfb, 0x21);	/* Mask all but cascade on the primary PIC */
     41	io_delay();
     42}
     43
     44/*
     45 * Reset IGNNE# if asserted in the FPU.
     46 */
     47static void reset_coprocessor(void)
     48{
     49	outb(0, 0xf0);
     50	io_delay();
     51	outb(0, 0xf1);
     52	io_delay();
     53}
     54
     55/*
     56 * Set up the GDT
     57 */
     58
     59struct gdt_ptr {
     60	u16 len;
     61	u32 ptr;
     62} __attribute__((packed));
     63
     64static void setup_gdt(void)
     65{
     66	/* There are machines which are known to not boot with the GDT
     67	   being 8-byte unaligned.  Intel recommends 16 byte alignment. */
     68	static const u64 boot_gdt[] __attribute__((aligned(16))) = {
     69		/* CS: code, read/execute, 4 GB, base 0 */
     70		[GDT_ENTRY_BOOT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
     71		/* DS: data, read/write, 4 GB, base 0 */
     72		[GDT_ENTRY_BOOT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
     73		/* TSS: 32-bit tss, 104 bytes, base 4096 */
     74		/* We only have a TSS here to keep Intel VT happy;
     75		   we don't actually use it for anything. */
     76		[GDT_ENTRY_BOOT_TSS] = GDT_ENTRY(0x0089, 4096, 103),
     77	};
     78	/* Xen HVM incorrectly stores a pointer to the gdt_ptr, instead
     79	   of the gdt_ptr contents.  Thus, make it static so it will
     80	   stay in memory, at least long enough that we switch to the
     81	   proper kernel GDT. */
     82	static struct gdt_ptr gdt;
     83
     84	gdt.len = sizeof(boot_gdt)-1;
     85	gdt.ptr = (u32)&boot_gdt + (ds() << 4);
     86
     87	asm volatile("lgdtl %0" : : "m" (gdt));
     88}
     89
     90/*
     91 * Set up the IDT
     92 */
     93static void setup_idt(void)
     94{
     95	static const struct gdt_ptr null_idt = {0, 0};
     96	asm volatile("lidtl %0" : : "m" (null_idt));
     97}
     98
     99/*
    100 * Actual invocation sequence
    101 */
    102void go_to_protected_mode(void)
    103{
    104	/* Hook before leaving real mode, also disables interrupts */
    105	realmode_switch_hook();
    106
    107	/* Enable the A20 gate */
    108	if (enable_a20()) {
    109		puts("A20 gate not responding, unable to boot...\n");
    110		die();
    111	}
    112
    113	/* Reset coprocessor (IGNNE#) */
    114	reset_coprocessor();
    115
    116	/* Mask all interrupts in the PIC */
    117	mask_all_interrupts();
    118
    119	/* Actual transition to protected mode... */
    120	setup_idt();
    121	setup_gdt();
    122	protected_mode_jump(boot_params.hdr.code32_start,
    123			    (u32)&boot_params + (ds() << 4));
    124}