apicdef.h (11310B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_APICDEF_H 3#define _ASM_X86_APICDEF_H 4 5/* 6 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 7 * 8 * Alan Cox <Alan.Cox@linux.org>, 1995. 9 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 10 */ 11 12#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 13#define APIC_DEFAULT_PHYS_BASE 0xfee00000 14 15/* 16 * This is the IO-APIC register space as specified 17 * by Intel docs: 18 */ 19#define IO_APIC_SLOT_SIZE 1024 20 21#define APIC_ID 0x20 22 23#define APIC_LVR 0x30 24#define APIC_LVR_MASK 0xFF00FF 25#define APIC_LVR_DIRECTED_EOI (1 << 24) 26#define GET_APIC_VERSION(x) ((x) & 0xFFu) 27#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 28#ifdef CONFIG_X86_32 29# define APIC_INTEGRATED(x) ((x) & 0xF0u) 30#else 31# define APIC_INTEGRATED(x) (1) 32#endif 33#define APIC_XAPIC(x) ((x) >= 0x14) 34#define APIC_EXT_SPACE(x) ((x) & 0x80000000) 35#define APIC_TASKPRI 0x80 36#define APIC_TPRI_MASK 0xFFu 37#define APIC_ARBPRI 0x90 38#define APIC_ARBPRI_MASK 0xFFu 39#define APIC_PROCPRI 0xA0 40#define APIC_EOI 0xB0 41#define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */ 42#define APIC_RRR 0xC0 43#define APIC_LDR 0xD0 44#define APIC_LDR_MASK (0xFFu << 24) 45#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 46#define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 47#define APIC_ALL_CPUS 0xFFu 48#define APIC_DFR 0xE0 49#define APIC_DFR_CLUSTER 0x0FFFFFFFul 50#define APIC_DFR_FLAT 0xFFFFFFFFul 51#define APIC_SPIV 0xF0 52#define APIC_SPIV_DIRECTED_EOI (1 << 12) 53#define APIC_SPIV_FOCUS_DISABLED (1 << 9) 54#define APIC_SPIV_APIC_ENABLED (1 << 8) 55#define APIC_ISR 0x100 56#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 57#define APIC_TMR 0x180 58#define APIC_IRR 0x200 59#define APIC_ESR 0x280 60#define APIC_ESR_SEND_CS 0x00001 61#define APIC_ESR_RECV_CS 0x00002 62#define APIC_ESR_SEND_ACC 0x00004 63#define APIC_ESR_RECV_ACC 0x00008 64#define APIC_ESR_SENDILL 0x00020 65#define APIC_ESR_RECVILL 0x00040 66#define APIC_ESR_ILLREGA 0x00080 67#define APIC_LVTCMCI 0x2f0 68#define APIC_ICR 0x300 69#define APIC_DEST_SELF 0x40000 70#define APIC_DEST_ALLINC 0x80000 71#define APIC_DEST_ALLBUT 0xC0000 72#define APIC_ICR_RR_MASK 0x30000 73#define APIC_ICR_RR_INVALID 0x00000 74#define APIC_ICR_RR_INPROG 0x10000 75#define APIC_ICR_RR_VALID 0x20000 76#define APIC_INT_LEVELTRIG 0x08000 77#define APIC_INT_ASSERT 0x04000 78#define APIC_ICR_BUSY 0x01000 79#define APIC_DEST_LOGICAL 0x00800 80#define APIC_DEST_PHYSICAL 0x00000 81#define APIC_DM_FIXED 0x00000 82#define APIC_DM_FIXED_MASK 0x00700 83#define APIC_DM_LOWEST 0x00100 84#define APIC_DM_SMI 0x00200 85#define APIC_DM_REMRD 0x00300 86#define APIC_DM_NMI 0x00400 87#define APIC_DM_INIT 0x00500 88#define APIC_DM_STARTUP 0x00600 89#define APIC_DM_EXTINT 0x00700 90#define APIC_VECTOR_MASK 0x000FF 91#define APIC_ICR2 0x310 92#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 93#define SET_APIC_DEST_FIELD(x) ((x) << 24) 94#define APIC_LVTT 0x320 95#define APIC_LVTTHMR 0x330 96#define APIC_LVTPC 0x340 97#define APIC_LVT0 0x350 98#define APIC_LVT_TIMER_ONESHOT (0 << 17) 99#define APIC_LVT_TIMER_PERIODIC (1 << 17) 100#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 101#define APIC_LVT_MASKED (1 << 16) 102#define APIC_LVT_LEVEL_TRIGGER (1 << 15) 103#define APIC_LVT_REMOTE_IRR (1 << 14) 104#define APIC_INPUT_POLARITY (1 << 13) 105#define APIC_SEND_PENDING (1 << 12) 106#define APIC_MODE_MASK 0x700 107#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 108#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 109#define APIC_MODE_FIXED 0x0 110#define APIC_MODE_NMI 0x4 111#define APIC_MODE_EXTINT 0x7 112#define APIC_LVT1 0x360 113#define APIC_LVTERR 0x370 114#define APIC_TMICT 0x380 115#define APIC_TMCCT 0x390 116#define APIC_TDCR 0x3E0 117#define APIC_SELF_IPI 0x3F0 118#define APIC_TDR_DIV_TMBASE (1 << 2) 119#define APIC_TDR_DIV_1 0xB 120#define APIC_TDR_DIV_2 0x0 121#define APIC_TDR_DIV_4 0x1 122#define APIC_TDR_DIV_8 0x2 123#define APIC_TDR_DIV_16 0x3 124#define APIC_TDR_DIV_32 0x8 125#define APIC_TDR_DIV_64 0x9 126#define APIC_TDR_DIV_128 0xA 127#define APIC_EFEAT 0x400 128#define APIC_ECTRL 0x410 129#define APIC_EILVTn(n) (0x500 + 0x10 * n) 130#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 131#define APIC_EILVT_NR_AMD_10H 4 132#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H 133#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 134#define APIC_EILVT_MSG_FIX 0x0 135#define APIC_EILVT_MSG_SMI 0x2 136#define APIC_EILVT_MSG_NMI 0x4 137#define APIC_EILVT_MSG_EXT 0x7 138#define APIC_EILVT_MASKED (1 << 16) 139 140#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 141#define APIC_BASE_MSR 0x800 142#define XAPIC_ENABLE (1UL << 11) 143#define X2APIC_ENABLE (1UL << 10) 144 145#ifdef CONFIG_X86_32 146# define MAX_IO_APICS 64 147# define MAX_LOCAL_APIC 256 148#else 149# define MAX_IO_APICS 128 150# define MAX_LOCAL_APIC 32768 151#endif 152 153/* 154 * All x86-64 systems are xAPIC compatible. 155 * In the following, "apicid" is a physical APIC ID. 156 */ 157#define XAPIC_DEST_CPUS_SHIFT 4 158#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) 159#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) 160#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) 161#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) 162#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 163#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 164 165/* 166 * the local APIC register structure, memory mapped. Not terribly well 167 * tested, but we might eventually use this one in the future - the 168 * problem why we cannot use it right now is the P5 APIC, it has an 169 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 170 */ 171#define u32 unsigned int 172 173struct local_apic { 174 175/*000*/ struct { u32 __reserved[4]; } __reserved_01; 176 177/*010*/ struct { u32 __reserved[4]; } __reserved_02; 178 179/*020*/ struct { /* APIC ID Register */ 180 u32 __reserved_1 : 24, 181 phys_apic_id : 4, 182 __reserved_2 : 4; 183 u32 __reserved[3]; 184 } id; 185 186/*030*/ const 187 struct { /* APIC Version Register */ 188 u32 version : 8, 189 __reserved_1 : 8, 190 max_lvt : 8, 191 __reserved_2 : 8; 192 u32 __reserved[3]; 193 } version; 194 195/*040*/ struct { u32 __reserved[4]; } __reserved_03; 196 197/*050*/ struct { u32 __reserved[4]; } __reserved_04; 198 199/*060*/ struct { u32 __reserved[4]; } __reserved_05; 200 201/*070*/ struct { u32 __reserved[4]; } __reserved_06; 202 203/*080*/ struct { /* Task Priority Register */ 204 u32 priority : 8, 205 __reserved_1 : 24; 206 u32 __reserved_2[3]; 207 } tpr; 208 209/*090*/ const 210 struct { /* Arbitration Priority Register */ 211 u32 priority : 8, 212 __reserved_1 : 24; 213 u32 __reserved_2[3]; 214 } apr; 215 216/*0A0*/ const 217 struct { /* Processor Priority Register */ 218 u32 priority : 8, 219 __reserved_1 : 24; 220 u32 __reserved_2[3]; 221 } ppr; 222 223/*0B0*/ struct { /* End Of Interrupt Register */ 224 u32 eoi; 225 u32 __reserved[3]; 226 } eoi; 227 228/*0C0*/ struct { u32 __reserved[4]; } __reserved_07; 229 230/*0D0*/ struct { /* Logical Destination Register */ 231 u32 __reserved_1 : 24, 232 logical_dest : 8; 233 u32 __reserved_2[3]; 234 } ldr; 235 236/*0E0*/ struct { /* Destination Format Register */ 237 u32 __reserved_1 : 28, 238 model : 4; 239 u32 __reserved_2[3]; 240 } dfr; 241 242/*0F0*/ struct { /* Spurious Interrupt Vector Register */ 243 u32 spurious_vector : 8, 244 apic_enabled : 1, 245 focus_cpu : 1, 246 __reserved_2 : 22; 247 u32 __reserved_3[3]; 248 } svr; 249 250/*100*/ struct { /* In Service Register */ 251/*170*/ u32 bitfield; 252 u32 __reserved[3]; 253 } isr [8]; 254 255/*180*/ struct { /* Trigger Mode Register */ 256/*1F0*/ u32 bitfield; 257 u32 __reserved[3]; 258 } tmr [8]; 259 260/*200*/ struct { /* Interrupt Request Register */ 261/*270*/ u32 bitfield; 262 u32 __reserved[3]; 263 } irr [8]; 264 265/*280*/ union { /* Error Status Register */ 266 struct { 267 u32 send_cs_error : 1, 268 receive_cs_error : 1, 269 send_accept_error : 1, 270 receive_accept_error : 1, 271 __reserved_1 : 1, 272 send_illegal_vector : 1, 273 receive_illegal_vector : 1, 274 illegal_register_address : 1, 275 __reserved_2 : 24; 276 u32 __reserved_3[3]; 277 } error_bits; 278 struct { 279 u32 errors; 280 u32 __reserved_3[3]; 281 } all_errors; 282 } esr; 283 284/*290*/ struct { u32 __reserved[4]; } __reserved_08; 285 286/*2A0*/ struct { u32 __reserved[4]; } __reserved_09; 287 288/*2B0*/ struct { u32 __reserved[4]; } __reserved_10; 289 290/*2C0*/ struct { u32 __reserved[4]; } __reserved_11; 291 292/*2D0*/ struct { u32 __reserved[4]; } __reserved_12; 293 294/*2E0*/ struct { u32 __reserved[4]; } __reserved_13; 295 296/*2F0*/ struct { u32 __reserved[4]; } __reserved_14; 297 298/*300*/ struct { /* Interrupt Command Register 1 */ 299 u32 vector : 8, 300 delivery_mode : 3, 301 destination_mode : 1, 302 delivery_status : 1, 303 __reserved_1 : 1, 304 level : 1, 305 trigger : 1, 306 __reserved_2 : 2, 307 shorthand : 2, 308 __reserved_3 : 12; 309 u32 __reserved_4[3]; 310 } icr1; 311 312/*310*/ struct { /* Interrupt Command Register 2 */ 313 union { 314 u32 __reserved_1 : 24, 315 phys_dest : 4, 316 __reserved_2 : 4; 317 u32 __reserved_3 : 24, 318 logical_dest : 8; 319 } dest; 320 u32 __reserved_4[3]; 321 } icr2; 322 323/*320*/ struct { /* LVT - Timer */ 324 u32 vector : 8, 325 __reserved_1 : 4, 326 delivery_status : 1, 327 __reserved_2 : 3, 328 mask : 1, 329 timer_mode : 1, 330 __reserved_3 : 14; 331 u32 __reserved_4[3]; 332 } lvt_timer; 333 334/*330*/ struct { /* LVT - Thermal Sensor */ 335 u32 vector : 8, 336 delivery_mode : 3, 337 __reserved_1 : 1, 338 delivery_status : 1, 339 __reserved_2 : 3, 340 mask : 1, 341 __reserved_3 : 15; 342 u32 __reserved_4[3]; 343 } lvt_thermal; 344 345/*340*/ struct { /* LVT - Performance Counter */ 346 u32 vector : 8, 347 delivery_mode : 3, 348 __reserved_1 : 1, 349 delivery_status : 1, 350 __reserved_2 : 3, 351 mask : 1, 352 __reserved_3 : 15; 353 u32 __reserved_4[3]; 354 } lvt_pc; 355 356/*350*/ struct { /* LVT - LINT0 */ 357 u32 vector : 8, 358 delivery_mode : 3, 359 __reserved_1 : 1, 360 delivery_status : 1, 361 polarity : 1, 362 remote_irr : 1, 363 trigger : 1, 364 mask : 1, 365 __reserved_2 : 15; 366 u32 __reserved_3[3]; 367 } lvt_lint0; 368 369/*360*/ struct { /* LVT - LINT1 */ 370 u32 vector : 8, 371 delivery_mode : 3, 372 __reserved_1 : 1, 373 delivery_status : 1, 374 polarity : 1, 375 remote_irr : 1, 376 trigger : 1, 377 mask : 1, 378 __reserved_2 : 15; 379 u32 __reserved_3[3]; 380 } lvt_lint1; 381 382/*370*/ struct { /* LVT - Error */ 383 u32 vector : 8, 384 __reserved_1 : 4, 385 delivery_status : 1, 386 __reserved_2 : 3, 387 mask : 1, 388 __reserved_3 : 15; 389 u32 __reserved_4[3]; 390 } lvt_error; 391 392/*380*/ struct { /* Timer Initial Count Register */ 393 u32 initial_count; 394 u32 __reserved_2[3]; 395 } timer_icr; 396 397/*390*/ const 398 struct { /* Timer Current Count Register */ 399 u32 curr_count; 400 u32 __reserved_2[3]; 401 } timer_ccr; 402 403/*3A0*/ struct { u32 __reserved[4]; } __reserved_16; 404 405/*3B0*/ struct { u32 __reserved[4]; } __reserved_17; 406 407/*3C0*/ struct { u32 __reserved[4]; } __reserved_18; 408 409/*3D0*/ struct { u32 __reserved[4]; } __reserved_19; 410 411/*3E0*/ struct { /* Timer Divide Configuration Register */ 412 u32 divisor : 4, 413 __reserved_1 : 28; 414 u32 __reserved_2[3]; 415 } timer_dcr; 416 417/*3F0*/ struct { u32 __reserved[4]; } __reserved_20; 418 419} __attribute__ ((packed)); 420 421#undef u32 422 423#ifdef CONFIG_X86_32 424 #define BAD_APICID 0xFFu 425#else 426 #define BAD_APICID 0xFFFFu 427#endif 428 429enum apic_delivery_modes { 430 APIC_DELIVERY_MODE_FIXED = 0, 431 APIC_DELIVERY_MODE_LOWESTPRIO = 1, 432 APIC_DELIVERY_MODE_SMI = 2, 433 APIC_DELIVERY_MODE_NMI = 4, 434 APIC_DELIVERY_MODE_INIT = 5, 435 APIC_DELIVERY_MODE_EXTINT = 7, 436}; 437 438#endif /* _ASM_X86_APICDEF_H */