cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

pgtable-2level.h (2815B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _ASM_X86_PGTABLE_2LEVEL_H
      3#define _ASM_X86_PGTABLE_2LEVEL_H
      4
      5#define pte_ERROR(e) \
      6	pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low)
      7#define pgd_ERROR(e) \
      8	pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e))
      9
     10/*
     11 * Certain architectures need to do special things when PTEs
     12 * within a page table are directly modified.  Thus, the following
     13 * hook is made available.
     14 */
     15static inline void native_set_pte(pte_t *ptep , pte_t pte)
     16{
     17	*ptep = pte;
     18}
     19
     20static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
     21{
     22	*pmdp = pmd;
     23}
     24
     25static inline void native_set_pud(pud_t *pudp, pud_t pud)
     26{
     27}
     28
     29static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
     30{
     31	native_set_pte(ptep, pte);
     32}
     33
     34static inline void native_pmd_clear(pmd_t *pmdp)
     35{
     36	native_set_pmd(pmdp, __pmd(0));
     37}
     38
     39static inline void native_pud_clear(pud_t *pudp)
     40{
     41}
     42
     43static inline void native_pte_clear(struct mm_struct *mm,
     44				    unsigned long addr, pte_t *xp)
     45{
     46	*xp = native_make_pte(0);
     47}
     48
     49#ifdef CONFIG_SMP
     50static inline pte_t native_ptep_get_and_clear(pte_t *xp)
     51{
     52	return __pte(xchg(&xp->pte_low, 0));
     53}
     54#else
     55#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
     56#endif
     57
     58#ifdef CONFIG_SMP
     59static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
     60{
     61	return __pmd(xchg((pmdval_t *)xp, 0));
     62}
     63#else
     64#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
     65#endif
     66
     67#ifdef CONFIG_SMP
     68static inline pud_t native_pudp_get_and_clear(pud_t *xp)
     69{
     70	return __pud(xchg((pudval_t *)xp, 0));
     71}
     72#else
     73#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
     74#endif
     75
     76/* Bit manipulation helper on pte/pgoff entry */
     77static inline unsigned long pte_bitop(unsigned long value, unsigned int rightshift,
     78				      unsigned long mask, unsigned int leftshift)
     79{
     80	return ((value >> rightshift) & mask) << leftshift;
     81}
     82
     83/* Encode and de-code a swap entry */
     84#define SWP_TYPE_BITS 5
     85#define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1)
     86
     87#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
     88
     89#define __swp_type(x)			(((x).val >> (_PAGE_BIT_PRESENT + 1)) \
     90					 & ((1U << SWP_TYPE_BITS) - 1))
     91#define __swp_offset(x)			((x).val >> SWP_OFFSET_SHIFT)
     92#define __swp_entry(type, offset)	((swp_entry_t) { \
     93					 ((type) << (_PAGE_BIT_PRESENT + 1)) \
     94					 | ((offset) << SWP_OFFSET_SHIFT) })
     95#define __pte_to_swp_entry(pte)		((swp_entry_t) { (pte).pte_low })
     96#define __swp_entry_to_pte(x)		((pte_t) { .pte = (x).val })
     97
     98/* No inverted PFNs on 2 level page tables */
     99
    100static inline u64 protnone_mask(u64 val)
    101{
    102	return 0;
    103}
    104
    105static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask)
    106{
    107	return val;
    108}
    109
    110static inline bool __pte_needs_invert(u64 val)
    111{
    112	return false;
    113}
    114
    115#endif /* _ASM_X86_PGTABLE_2LEVEL_H */