cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pgtable_32.h (2346B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _ASM_X86_PGTABLE_32_H
      3#define _ASM_X86_PGTABLE_32_H
      4
      5#include <asm/pgtable_32_types.h>
      6
      7/*
      8 * The Linux memory management assumes a three-level page table setup. On
      9 * the i386, we use that, but "fold" the mid level into the top-level page
     10 * table, so that we physically have the same two-level page table as the
     11 * i386 mmu expects.
     12 *
     13 * This file contains the functions and defines necessary to modify and use
     14 * the i386 page table tree.
     15 */
     16#ifndef __ASSEMBLY__
     17#include <asm/processor.h>
     18#include <linux/threads.h>
     19#include <asm/paravirt.h>
     20
     21#include <linux/bitops.h>
     22#include <linux/list.h>
     23#include <linux/spinlock.h>
     24
     25struct mm_struct;
     26struct vm_area_struct;
     27
     28extern pgd_t swapper_pg_dir[1024];
     29extern pgd_t initial_page_table[1024];
     30extern pmd_t initial_pg_pmd[];
     31
     32void paging_init(void);
     33void sync_initial_page_table(void);
     34
     35#ifdef CONFIG_X86_PAE
     36# include <asm/pgtable-3level.h>
     37#else
     38# include <asm/pgtable-2level.h>
     39#endif
     40
     41/* Clear a kernel PTE and flush it from the TLB */
     42#define kpte_clear_flush(ptep, vaddr)		\
     43do {						\
     44	pte_clear(&init_mm, (vaddr), (ptep));	\
     45	flush_tlb_one_kernel((vaddr));		\
     46} while (0)
     47
     48#endif /* !__ASSEMBLY__ */
     49
     50/*
     51 * kern_addr_valid() is (1) for FLATMEM and (0) for SPARSEMEM
     52 */
     53#ifdef CONFIG_FLATMEM
     54#define kern_addr_valid(addr)	(1)
     55#else
     56#define kern_addr_valid(kaddr)	(0)
     57#endif
     58
     59/*
     60 * This is used to calculate the .brk reservation for initial pagetables.
     61 * Enough space is reserved to allocate pagetables sufficient to cover all
     62 * of LOWMEM_PAGES, which is an upper bound on the size of the direct map of
     63 * lowmem.
     64 *
     65 * With PAE paging (PTRS_PER_PMD > 1), we allocate PTRS_PER_PGD == 4 pages for
     66 * the PMD's in addition to the pages required for the last level pagetables.
     67 */
     68#if PTRS_PER_PMD > 1
     69#define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD)
     70#else
     71#define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD)
     72#endif
     73
     74/*
     75 * Number of possible pages in the lowmem region.
     76 *
     77 * We shift 2 by 31 instead of 1 by 32 to the left in order to avoid a
     78 * gas warning about overflowing shift count when gas has been compiled
     79 * with only a host target support using a 32-bit type for internal
     80 * representation.
     81 */
     82#define LOWMEM_PAGES ((((_ULL(2)<<31) - __PAGE_OFFSET) >> PAGE_SHIFT))
     83
     84#endif /* _ASM_X86_PGTABLE_32_H */