cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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serial.h (1137B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _ASM_X86_SERIAL_H
      3#define _ASM_X86_SERIAL_H
      4
      5/*
      6 * This assumes you have a 1.8432 MHz clock for your UART.
      7 *
      8 * It'd be nice if someone built a serial card with a 24.576 MHz
      9 * clock, since the 16550A is capable of handling a top speed of 1.5
     10 * megabits/second; but this requires a faster clock.
     11 */
     12#define BASE_BAUD (1843200/16)
     13
     14/* Standard COM flags (except for COM4, because of the 8514 problem) */
     15#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
     16# define STD_COMX_FLAGS	(UPF_BOOT_AUTOCONF |	UPF_SKIP_TEST	| UPF_AUTO_IRQ)
     17# define STD_COM4_FLAGS	(UPF_BOOT_AUTOCONF |	0		| UPF_AUTO_IRQ)
     18#else
     19# define STD_COMX_FLAGS	(UPF_BOOT_AUTOCONF |	UPF_SKIP_TEST	| 0		)
     20# define STD_COM4_FLAGS	(UPF_BOOT_AUTOCONF |	0		| 0		)
     21#endif
     22
     23#define SERIAL_PORT_DFNS								\
     24	/* UART		CLK		PORT	IRQ	FLAGS			    */	\
     25	{ .uart = 0,	BASE_BAUD,	0x3F8,	4,	STD_COMX_FLAGS	}, /* ttyS0 */	\
     26	{ .uart = 0,	BASE_BAUD,	0x2F8,	3,	STD_COMX_FLAGS	}, /* ttyS1 */	\
     27	{ .uart = 0,	BASE_BAUD,	0x3E8,	4,	STD_COMX_FLAGS	}, /* ttyS2 */	\
     28	{ .uart = 0,	BASE_BAUD,	0x2E8,	3,	STD_COM4_FLAGS	}, /* ttyS3 */
     29
     30#endif /* _ASM_X86_SERIAL_H */