cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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user.h (2257B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _ASM_X86_USER_H
      3#define _ASM_X86_USER_H
      4
      5#ifdef CONFIG_X86_32
      6# include <asm/user_32.h>
      7#else
      8# include <asm/user_64.h>
      9#endif
     10
     11#include <asm/types.h>
     12
     13struct user_ymmh_regs {
     14	/* 16 * 16 bytes for each YMMH-reg */
     15	__u32 ymmh_space[64];
     16};
     17
     18struct user_xstate_header {
     19	__u64 xfeatures;
     20	__u64 reserved1[2];
     21	__u64 reserved2[5];
     22};
     23
     24/*
     25 * The structure layout of user_xstateregs, used for exporting the
     26 * extended register state through ptrace and core-dump (NT_X86_XSTATE note)
     27 * interfaces will be same as the memory layout of xsave used by the processor
     28 * (except for the bytes 464..511, which can be used by the software) and hence
     29 * the size of this structure varies depending on the features supported by the
     30 * processor and OS. The size of the structure that users need to use can be
     31 * obtained by doing:
     32 *     cpuid_count(0xd, 0, &eax, &ptrace_xstateregs_struct_size, &ecx, &edx);
     33 * i.e., cpuid.(eax=0xd,ecx=0).ebx will be the size that user (debuggers, etc.)
     34 * need to use.
     35 *
     36 * For now, only the first 8 bytes of the software usable bytes[464..471] will
     37 * be used and will be set to OS enabled xstate mask (which is same as the
     38 * 64bit mask returned by the xgetbv's xCR0).  Users (analyzing core dump
     39 * remotely, etc.) can use this mask as well as the mask saved in the
     40 * xstate_hdr bytes and interpret what states the processor/OS supports
     41 * and what states are in modified/initialized conditions for the
     42 * particular process/thread.
     43 *
     44 * Also when the user modifies certain state FP/SSE/etc through the
     45 * ptrace interface, they must ensure that the header.xfeatures
     46 * bytes[512..519] of the memory layout are updated correspondingly.
     47 * i.e., for example when FP state is modified to a non-init state,
     48 * header.xfeatures's bit 0 must be set to '1', when SSE is modified to
     49 * non-init state, header.xfeatures's bit 1 must to be set to '1', etc.
     50 */
     51#define USER_XSTATE_FX_SW_WORDS 6
     52#define USER_XSTATE_XCR0_WORD	0
     53
     54struct user_xstateregs {
     55	struct {
     56		__u64 fpx_space[58];
     57		__u64 xstate_fx_sw[USER_XSTATE_FX_SW_WORDS];
     58	} i387;
     59	struct user_xstate_header header;
     60	struct user_ymmh_regs ymmh;
     61	/* further processor state extensions go here */
     62};
     63
     64#endif /* _ASM_X86_USER_H */