cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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interface_32.h (2991B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/******************************************************************************
      3 * arch-x86_32.h
      4 *
      5 * Guest OS interface to x86 32-bit Xen.
      6 *
      7 * Copyright (c) 2004, K A Fraser
      8 */
      9
     10#ifndef _ASM_X86_XEN_INTERFACE_32_H
     11#define _ASM_X86_XEN_INTERFACE_32_H
     12
     13
     14/*
     15 * These flat segments are in the Xen-private section of every GDT. Since these
     16 * are also present in the initial GDT, many OSes will be able to avoid
     17 * installing their own GDT.
     18 */
     19#define FLAT_RING1_CS 0xe019    /* GDT index 259 */
     20#define FLAT_RING1_DS 0xe021    /* GDT index 260 */
     21#define FLAT_RING1_SS 0xe021    /* GDT index 260 */
     22#define FLAT_RING3_CS 0xe02b    /* GDT index 261 */
     23#define FLAT_RING3_DS 0xe033    /* GDT index 262 */
     24#define FLAT_RING3_SS 0xe033    /* GDT index 262 */
     25
     26#define FLAT_KERNEL_CS FLAT_RING1_CS
     27#define FLAT_KERNEL_DS FLAT_RING1_DS
     28#define FLAT_KERNEL_SS FLAT_RING1_SS
     29#define FLAT_USER_CS    FLAT_RING3_CS
     30#define FLAT_USER_DS    FLAT_RING3_DS
     31#define FLAT_USER_SS    FLAT_RING3_SS
     32
     33/* And the trap vector is... */
     34#define TRAP_INSTR "int $0x82"
     35
     36#define __MACH2PHYS_VIRT_START 0xF5800000
     37#define __MACH2PHYS_VIRT_END   0xF6800000
     38
     39#define __MACH2PHYS_SHIFT      2
     40
     41/*
     42 * Virtual addresses beyond this are not modifiable by guest OSes. The
     43 * machine->physical mapping table starts at this address, read-only.
     44 */
     45#define __HYPERVISOR_VIRT_START 0xF5800000
     46
     47#ifndef __ASSEMBLY__
     48
     49struct cpu_user_regs {
     50    uint32_t ebx;
     51    uint32_t ecx;
     52    uint32_t edx;
     53    uint32_t esi;
     54    uint32_t edi;
     55    uint32_t ebp;
     56    uint32_t eax;
     57    uint16_t error_code;    /* private */
     58    uint16_t entry_vector;  /* private */
     59    uint32_t eip;
     60    uint16_t cs;
     61    uint8_t  saved_upcall_mask;
     62    uint8_t  _pad0;
     63    uint32_t eflags;        /* eflags.IF == !saved_upcall_mask */
     64    uint32_t esp;
     65    uint16_t ss, _pad1;
     66    uint16_t es, _pad2;
     67    uint16_t ds, _pad3;
     68    uint16_t fs, _pad4;
     69    uint16_t gs, _pad5;
     70};
     71DEFINE_GUEST_HANDLE_STRUCT(cpu_user_regs);
     72
     73typedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */
     74
     75struct arch_vcpu_info {
     76    unsigned long cr2;
     77    unsigned long pad[5]; /* sizeof(struct vcpu_info) == 64 */
     78};
     79
     80struct xen_callback {
     81	unsigned long cs;
     82	unsigned long eip;
     83};
     84typedef struct xen_callback xen_callback_t;
     85
     86#define XEN_CALLBACK(__cs, __eip)				\
     87	((struct xen_callback){ .cs = (__cs), .eip = (unsigned long)(__eip) })
     88#endif /* !__ASSEMBLY__ */
     89
     90
     91/*
     92 * Page-directory addresses above 4GB do not fit into architectural %cr3.
     93 * When accessing %cr3, or equivalent field in vcpu_guest_context, guests
     94 * must use the following accessor macros to pack/unpack valid MFNs.
     95 *
     96 * Note that Xen is using the fact that the pagetable base is always
     97 * page-aligned, and putting the 12 MSB of the address into the 12 LSB
     98 * of cr3.
     99 */
    100#define xen_pfn_to_cr3(pfn) (((unsigned)(pfn) << 12) | ((unsigned)(pfn) >> 20))
    101#define xen_cr3_to_pfn(cr3) (((unsigned)(cr3) >> 12) | ((unsigned)(cr3) << 20))
    102
    103#endif /* _ASM_X86_XEN_INTERFACE_32_H */