cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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lapic.h (8105B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef __KVM_X86_LAPIC_H
      3#define __KVM_X86_LAPIC_H
      4
      5#include <kvm/iodev.h>
      6
      7#include <linux/kvm_host.h>
      8
      9#include "hyperv.h"
     10
     11#define KVM_APIC_INIT		0
     12#define KVM_APIC_SIPI		1
     13#define KVM_APIC_LVT_NUM	6
     14
     15#define APIC_SHORT_MASK			0xc0000
     16#define APIC_DEST_NOSHORT		0x0
     17#define APIC_DEST_MASK			0x800
     18
     19#define APIC_BUS_CYCLE_NS       1
     20#define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)
     21
     22#define APIC_BROADCAST			0xFF
     23#define X2APIC_BROADCAST		0xFFFFFFFFul
     24
     25enum lapic_mode {
     26	LAPIC_MODE_DISABLED = 0,
     27	LAPIC_MODE_INVALID = X2APIC_ENABLE,
     28	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
     29	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
     30};
     31
     32struct kvm_timer {
     33	struct hrtimer timer;
     34	s64 period; 				/* unit: ns */
     35	ktime_t target_expiration;
     36	u32 timer_mode;
     37	u32 timer_mode_mask;
     38	u64 tscdeadline;
     39	u64 expired_tscdeadline;
     40	u32 timer_advance_ns;
     41	atomic_t pending;			/* accumulated triggered timers */
     42	bool hv_timer_in_use;
     43};
     44
     45struct kvm_lapic {
     46	unsigned long base_address;
     47	struct kvm_io_device dev;
     48	struct kvm_timer lapic_timer;
     49	u32 divide_count;
     50	struct kvm_vcpu *vcpu;
     51	bool sw_enabled;
     52	bool irr_pending;
     53	bool lvt0_in_nmi_mode;
     54	/* Number of bits set in ISR. */
     55	s16 isr_count;
     56	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
     57	int highest_isr_cache;
     58	/**
     59	 * APIC register page.  The layout matches the register layout seen by
     60	 * the guest 1:1, because it is accessed by the vmx microcode.
     61	 * Note: Only one register, the TPR, is used by the microcode.
     62	 */
     63	void *regs;
     64	gpa_t vapic_addr;
     65	struct gfn_to_hva_cache vapic_cache;
     66	unsigned long pending_events;
     67	unsigned int sipi_vector;
     68};
     69
     70struct dest_map;
     71
     72int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
     73void kvm_free_lapic(struct kvm_vcpu *vcpu);
     74
     75int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
     76int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
     77int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
     78int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
     79void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
     80u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
     81void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
     82void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
     83void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
     84u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
     85void kvm_recalculate_apic_map(struct kvm *kvm);
     86void kvm_apic_set_version(struct kvm_vcpu *vcpu);
     87bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
     88			   int shorthand, unsigned int dest, int dest_mode);
     89int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
     90void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
     91bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
     92bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
     93void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
     94int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
     95		     struct dest_map *dest_map);
     96int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
     97void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
     98
     99bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
    100		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
    101void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
    102
    103u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
    104int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
    105int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
    106int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
    107enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
    108int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
    109
    110u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
    111void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
    112
    113void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
    114void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
    115
    116int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
    117void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
    118void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
    119
    120int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
    121int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
    122int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
    123
    124int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
    125int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
    126
    127int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
    128void kvm_lapic_exit(void);
    129
    130#define VEC_POS(v) ((v) & (32 - 1))
    131#define REG_POS(v) (((v) >> 5) << 4)
    132
    133static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
    134{
    135	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
    136}
    137
    138static inline void kvm_lapic_set_vector(int vec, void *bitmap)
    139{
    140	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
    141}
    142
    143static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
    144{
    145	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
    146	/*
    147	 * irr_pending must be true if any interrupt is pending; set it after
    148	 * APIC_IRR to avoid race with apic_clear_irr
    149	 */
    150	apic->irr_pending = true;
    151}
    152
    153static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
    154{
    155	return *((u32 *) (regs + reg_off));
    156}
    157
    158static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
    159{
    160	return __kvm_lapic_get_reg(apic->regs, reg_off);
    161}
    162
    163DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
    164
    165static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
    166{
    167	if (static_branch_unlikely(&kvm_has_noapic_vcpu))
    168		return vcpu->arch.apic;
    169	return true;
    170}
    171
    172extern struct static_key_false_deferred apic_hw_disabled;
    173
    174static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
    175{
    176	if (static_branch_unlikely(&apic_hw_disabled.key))
    177		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
    178	return MSR_IA32_APICBASE_ENABLE;
    179}
    180
    181extern struct static_key_false_deferred apic_sw_disabled;
    182
    183static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
    184{
    185	if (static_branch_unlikely(&apic_sw_disabled.key))
    186		return apic->sw_enabled;
    187	return true;
    188}
    189
    190static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
    191{
    192	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
    193}
    194
    195static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
    196{
    197	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
    198}
    199
    200static inline int apic_x2apic_mode(struct kvm_lapic *apic)
    201{
    202	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
    203}
    204
    205static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
    206{
    207	return vcpu->arch.apic && vcpu->arch.apicv_active;
    208}
    209
    210static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
    211{
    212	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
    213}
    214
    215static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
    216{
    217	return (irq->delivery_mode == APIC_DM_LOWEST ||
    218			irq->msi_redir_hint);
    219}
    220
    221static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
    222{
    223	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
    224}
    225
    226bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
    227
    228void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
    229
    230void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
    231			      unsigned long *vcpu_bitmap);
    232
    233bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
    234			struct kvm_vcpu **dest_vcpu);
    235int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
    236			const unsigned long *bitmap, u32 bitmap_size);
    237void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
    238void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
    239void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
    240bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
    241void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
    242bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
    243
    244static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
    245{
    246	return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
    247}
    248
    249static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
    250{
    251	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
    252}
    253
    254#endif