cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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status_w.h (2553B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*---------------------------------------------------------------------------+
      3 |  status_w.h                                                               |
      4 |                                                                           |
      5 | Copyright (C) 1992,1993                                                   |
      6 |                       W. Metzenthen, 22 Parker St, Ormond, Vic 3163,      |
      7 |                       Australia.  E-mail   billm@vaxc.cc.monash.edu.au    |
      8 |                                                                           |
      9 +---------------------------------------------------------------------------*/
     10
     11#ifndef _STATUS_H_
     12#define _STATUS_H_
     13
     14#include "fpu_emu.h"		/* for definition of PECULIAR_486 */
     15
     16#ifdef __ASSEMBLY__
     17#define	Const__(x)	$##x
     18#else
     19#define	Const__(x)	x
     20#endif
     21
     22#define SW_Backward    	Const__(0x8000)	/* backward compatibility */
     23#define SW_C3		Const__(0x4000)	/* condition bit 3 */
     24#define SW_Top		Const__(0x3800)	/* top of stack */
     25#define SW_Top_Shift 	Const__(11)	/* shift for top of stack bits */
     26#define SW_C2		Const__(0x0400)	/* condition bit 2 */
     27#define SW_C1		Const__(0x0200)	/* condition bit 1 */
     28#define SW_C0		Const__(0x0100)	/* condition bit 0 */
     29#define SW_Summary     	Const__(0x0080)	/* exception summary */
     30#define SW_Stack_Fault	Const__(0x0040)	/* stack fault */
     31#define SW_Precision   	Const__(0x0020)	/* loss of precision */
     32#define SW_Underflow   	Const__(0x0010)	/* underflow */
     33#define SW_Overflow    	Const__(0x0008)	/* overflow */
     34#define SW_Zero_Div    	Const__(0x0004)	/* divide by zero */
     35#define SW_Denorm_Op   	Const__(0x0002)	/* denormalized operand */
     36#define SW_Invalid     	Const__(0x0001)	/* invalid operation */
     37
     38#define SW_Exc_Mask     Const__(0x27f)	/* Status word exception bit mask */
     39
     40#ifndef __ASSEMBLY__
     41
     42#define COMP_A_gt_B	1
     43#define COMP_A_eq_B	2
     44#define COMP_A_lt_B	3
     45#define COMP_No_Comp	4
     46#define COMP_Denormal   0x20
     47#define COMP_NaN	0x40
     48#define COMP_SNaN	0x80
     49
     50#define status_word() \
     51  ((partial_status & ~SW_Top & 0xffff) | ((top << SW_Top_Shift) & SW_Top))
     52static inline void setcc(int cc)
     53{
     54	partial_status &= ~(SW_C0 | SW_C1 | SW_C2 | SW_C3);
     55	partial_status |= (cc) & (SW_C0 | SW_C1 | SW_C2 | SW_C3);
     56}
     57
     58#ifdef PECULIAR_486
     59   /* Default, this conveys no information, but an 80486 does it. */
     60   /* Clear the SW_C1 bit, "other bits undefined". */
     61#  define clear_C1()  { partial_status &= ~SW_C1; }
     62# else
     63#  define clear_C1()
     64#endif /* PECULIAR_486 */
     65
     66#endif /* __ASSEMBLY__ */
     67
     68#endif /* _STATUS_H_ */