cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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reboot.S (4290B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#include <linux/linkage.h>
      3#include <asm/segment.h>
      4#include <asm/page_types.h>
      5#include <asm/processor-flags.h>
      6#include <asm/msr-index.h>
      7#include "realmode.h"
      8
      9/*
     10 * The following code and data reboots the machine by switching to real
     11 * mode and jumping to the BIOS reset entry point, as if the CPU has
     12 * really been reset.  The previous version asked the keyboard
     13 * controller to pulse the CPU reset line, which is more thorough, but
     14 * doesn't work with at least one type of 486 motherboard.  It is easy
     15 * to stop this code working; hence the copious comments.
     16 *
     17 * This code is called with the restart type (0 = BIOS, 1 = APM) in
     18 * the primary argument register (%eax for 32 bit, %edi for 64 bit).
     19 */
     20	.section ".text32", "ax"
     21	.code32
     22SYM_CODE_START(machine_real_restart_asm)
     23
     24#ifdef CONFIG_X86_64
     25	/* Switch to trampoline GDT as it is guaranteed < 4 GiB */
     26	movl	$__KERNEL_DS, %eax
     27	movl	%eax, %ds
     28	lgdtl	pa_tr_gdt
     29
     30	/* Disable paging to drop us out of long mode */
     31	movl	%cr0, %eax
     32	andl	$~X86_CR0_PG, %eax
     33	movl	%eax, %cr0
     34	ljmpl	$__KERNEL32_CS, $pa_machine_real_restart_paging_off
     35
     36SYM_INNER_LABEL(machine_real_restart_paging_off, SYM_L_GLOBAL)
     37	xorl	%eax, %eax
     38	xorl	%edx, %edx
     39	movl	$MSR_EFER, %ecx
     40	wrmsr
     41
     42	movl	%edi, %eax
     43	
     44#endif /* CONFIG_X86_64 */
     45	
     46	/* Set up the IDT for real mode. */
     47	lidtl	pa_machine_real_restart_idt
     48
     49	/*
     50	 * Set up a GDT from which we can load segment descriptors for real
     51	 * mode.  The GDT is not used in real mode; it is just needed here to
     52	 * prepare the descriptors.
     53	 */
     54	lgdtl	pa_machine_real_restart_gdt
     55
     56	/*
     57	 * Load the data segment registers with 16-bit compatible values
     58	 */
     59	movl	$16, %ecx
     60	movl	%ecx, %ds
     61	movl	%ecx, %es
     62	movl	%ecx, %fs
     63	movl	%ecx, %gs
     64	movl	%ecx, %ss
     65	ljmpw	$8, $1f
     66SYM_CODE_END(machine_real_restart_asm)
     67
     68/*
     69 * This is 16-bit protected mode code to disable paging and the cache,
     70 * switch to real mode and jump to the BIOS reset code.
     71 *
     72 * The instruction that switches to real mode by writing to CR0 must be
     73 * followed immediately by a far jump instruction, which set CS to a
     74 * valid value for real mode, and flushes the prefetch queue to avoid
     75 * running instructions that have already been decoded in protected
     76 * mode.
     77 *
     78 * Clears all the flags except ET, especially PG (paging), PE
     79 * (protected-mode enable) and TS (task switch for coprocessor state
     80 * save).  Flushes the TLB after paging has been disabled.  Sets CD and
     81 * NW, to disable the cache on a 486, and invalidates the cache.  This
     82 * is more like the state of a 486 after reset.  I don't know if
     83 * something else should be done for other chips.
     84 *
     85 * More could be done here to set up the registers as if a CPU reset had
     86 * occurred; hopefully real BIOSs don't assume much.  This is not the
     87 * actual BIOS entry point, anyway (that is at 0xfffffff0).
     88 *
     89 * Most of this work is probably excessive, but it is what is tested.
     90 */
     91	.text
     92	.code16
     93
     94	.balign	16
     95machine_real_restart_asm16:
     961:
     97	xorl	%ecx, %ecx
     98	movl	%cr0, %edx
     99	andl	$0x00000011, %edx
    100	orl	$0x60000000, %edx
    101	movl	%edx, %cr0
    102	movl	%ecx, %cr3
    103	movl	%cr0, %edx
    104	testl	$0x60000000, %edx	/* If no cache bits -> no wbinvd */
    105	jz	2f
    106	wbinvd
    1072:
    108	andb	$0x10, %dl
    109	movl	%edx, %cr0
    110	LJMPW_RM(3f)
    1113:
    112	andw	%ax, %ax
    113	jz	bios
    114
    115apm:
    116	movw	$0x1000, %ax
    117	movw	%ax, %ss
    118	movw	$0xf000, %sp
    119	movw	$0x5307, %ax
    120	movw	$0x0001, %bx
    121	movw	$0x0003, %cx
    122	int	$0x15
    123	/* This should never return... */
    124
    125bios:
    126	ljmpw	$0xf000, $0xfff0
    127
    128	.section ".rodata", "a"
    129
    130	.balign	16
    131SYM_DATA_START(machine_real_restart_idt)
    132	.word	0xffff		/* Length - real mode default value */
    133	.long	0		/* Base - real mode default value */
    134SYM_DATA_END(machine_real_restart_idt)
    135
    136	.balign	16
    137SYM_DATA_START(machine_real_restart_gdt)
    138	/* Self-pointer */
    139	.word	0xffff		/* Length - real mode default value */
    140	.long	pa_machine_real_restart_gdt
    141	.word	0
    142
    143	/*
    144	 * 16-bit code segment pointing to real_mode_seg
    145	 * Selector value 8
    146	 */
    147	.word	0xffff		/* Limit */
    148	.long	0x9b000000 + pa_real_mode_base
    149	.word	0
    150
    151	/*
    152	 * 16-bit data segment with the selector value 16 = 0x10 and
    153	 * base value 0x100; since this is consistent with real mode
    154	 * semantics we don't have to reload the segments once CR0.PE = 0.
    155	 */
    156	.quad	GDT_ENTRY(0x0093, 0x100, 0xffff)
    157SYM_DATA_END(machine_real_restart_gdt)