cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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core.h (1069B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright (C) 2019 Cadence Design Systems Inc. */
      3
      4#ifndef _ASM_XTENSA_CORE_H
      5#define _ASM_XTENSA_CORE_H
      6
      7#include <variant/core.h>
      8
      9#ifndef XCHAL_HAVE_EXCLUSIVE
     10#define XCHAL_HAVE_EXCLUSIVE 0
     11#endif
     12
     13#ifndef XCHAL_HAVE_EXTERN_REGS
     14#define XCHAL_HAVE_EXTERN_REGS 0
     15#endif
     16
     17#ifndef XCHAL_HAVE_MPU
     18#define XCHAL_HAVE_MPU 0
     19#endif
     20
     21#ifndef XCHAL_HAVE_VECBASE
     22#define XCHAL_HAVE_VECBASE 0
     23#endif
     24
     25#ifndef XCHAL_SPANNING_WAY
     26#define XCHAL_SPANNING_WAY 0
     27#endif
     28
     29#if XCHAL_HAVE_WINDOWED
     30#if defined(CONFIG_USER_ABI_DEFAULT) || defined(CONFIG_USER_ABI_CALL0_PROBE)
     31/* Whether windowed ABI is supported in userspace. */
     32#define USER_SUPPORT_WINDOWED
     33#endif
     34#if defined(__XTENSA_WINDOWED_ABI__) || defined(USER_SUPPORT_WINDOWED)
     35/* Whether windowed ABI is supported either in userspace or in the kernel. */
     36#define SUPPORT_WINDOWED
     37#endif
     38#endif
     39
     40/* Xtensa ABI requires stack alignment to be at least 16 */
     41#if XCHAL_DATA_WIDTH > 16
     42#define XTENSA_STACK_ALIGNMENT	XCHAL_DATA_WIDTH
     43#else
     44#define XTENSA_STACK_ALIGNMENT	16
     45#endif
     46
     47#endif