cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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traps.h (3405B)

      1/*
      2 * arch/xtensa/include/asm/traps.h
      3 *
      4 * This file is subject to the terms and conditions of the GNU General Public
      5 * License.  See the file "COPYING" in the main directory of this archive
      6 * for more details.
      7 *
      8 * Copyright (C) 2012 Tensilica Inc.
      9 */
     10#ifndef _XTENSA_TRAPS_H
     11#define _XTENSA_TRAPS_H
     12
     13#include <asm/ptrace.h>
     14
     15typedef void xtensa_exception_handler(struct pt_regs *regs);
     16
     17/*
     18 * Per-CPU exception handling data structure.
     19 * EXCSAVE1 points to it.
     20 */
     21struct exc_table {
     22	/* Kernel Stack */
     23	void *kstk;
     24	/* Double exception save area for a0 */
     25	unsigned long double_save;
     26	/* Fixup handler */
     27	void *fixup;
     28	/* For passing a parameter to fixup */
     29	void *fixup_param;
     30#if XTENSA_HAVE_COPROCESSORS
     31	/* Pointers to owner struct thread_info */
     32	struct thread_info *coprocessor_owner[XCHAL_CP_MAX];
     33#endif
     34	/* Fast user exception handlers */
     35	void *fast_user_handler[EXCCAUSE_N];
     36	/* Fast kernel exception handlers */
     37	void *fast_kernel_handler[EXCCAUSE_N];
     38	/* Default C-Handlers */
     39	xtensa_exception_handler *default_handler[EXCCAUSE_N];
     40};
     41
     42DECLARE_PER_CPU(struct exc_table, exc_table);
     43
     44xtensa_exception_handler *
     45__init trap_set_handler(int cause, xtensa_exception_handler *handler);
     46
     47asmlinkage void fast_illegal_instruction_user(void);
     48asmlinkage void fast_syscall_user(void);
     49asmlinkage void fast_alloca(void);
     50asmlinkage void fast_unaligned(void);
     51asmlinkage void fast_second_level_miss(void);
     52asmlinkage void fast_store_prohibited(void);
     53asmlinkage void fast_coprocessor(void);
     54
     55asmlinkage void kernel_exception(void);
     56asmlinkage void user_exception(void);
     57asmlinkage void system_call(struct pt_regs *regs);
     58
     59void do_IRQ(int hwirq, struct pt_regs *regs);
     60void do_page_fault(struct pt_regs *regs);
     61void do_unhandled(struct pt_regs *regs);
     62
     63/* Initialize minimal exc_table structure sufficient for basic paging */
     64static inline void __init early_trap_init(void)
     65{
     66	static struct exc_table init_exc_table __initdata = {
     67		.fast_kernel_handler[EXCCAUSE_DTLB_MISS] =
     68			fast_second_level_miss,
     69	};
     70	xtensa_set_sr(&init_exc_table, excsave1);
     71}
     72
     73void secondary_trap_init(void);
     74
     75static inline void spill_registers(void)
     76{
     77#if defined(__XTENSA_WINDOWED_ABI__)
     78#if XCHAL_NUM_AREGS > 16
     79	__asm__ __volatile__ (
     80		"	call8	1f\n"
     81		"	_j	2f\n"
     82		"	retw\n"
     83		"	.align	4\n"
     84		"1:\n"
     85#if XCHAL_NUM_AREGS == 32
     86		"	_entry	a1, 32\n"
     87		"	addi	a8, a0, 3\n"
     88		"	_entry	a1, 16\n"
     89		"	mov	a12, a12\n"
     90		"	retw\n"
     91#else
     92		"	_entry	a1, 48\n"
     93		"	call12	1f\n"
     94		"	retw\n"
     95		"	.align	4\n"
     96		"1:\n"
     97		"	.rept	(" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n"
     98		"	_entry	a1, 48\n"
     99		"	mov	a12, a0\n"
    100		"	.endr\n"
    101		"	_entry	a1, 16\n"
    102#if XCHAL_NUM_AREGS % 12 == 0
    103		"	mov	a12, a12\n"
    104#elif XCHAL_NUM_AREGS % 12 == 4
    105		"	mov	a4, a4\n"
    106#elif XCHAL_NUM_AREGS % 12 == 8
    107		"	mov	a8, a8\n"
    108#endif
    109		"	retw\n"
    110#endif
    111		"2:\n"
    112		: : : "a8", "a9", "memory");
    113#else
    114	__asm__ __volatile__ (
    115		"	mov	a12, a12\n"
    116		: : : "memory");
    117#endif
    118#endif
    119}
    120
    121struct debug_table {
    122	/* Pointer to debug exception handler */
    123	void (*debug_exception)(void);
    124	/* Temporary register save area */
    125	unsigned long debug_save[1];
    126#ifdef CONFIG_HAVE_HW_BREAKPOINT
    127	/* Save area for DBREAKC registers */
    128	unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
    129	/* Saved ICOUNT register */
    130	unsigned long icount_save;
    131	/* Saved ICOUNTLEVEL register */
    132	unsigned long icount_level_save;
    133#endif
    134};
    135
    136void debug_exception(void);
    137
    138#endif /* _XTENSA_TRAPS_H */