cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mxhead.S (1341B)


      1/*
      2 * Xtensa Secondary Processors startup code.
      3 *
      4 * This file is subject to the terms and conditions of the GNU General Public
      5 * License.  See the file "COPYING" in the main directory of this archive
      6 * for more details.
      7 *
      8 * Copyright (C) 2001 - 2013 Tensilica Inc.
      9 *
     10 * Joe Taylor <joe@tensilica.com>
     11 * Chris Zankel <chris@zankel.net>
     12 * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
     13 * Pete Delaney <piet@tensilica.com>
     14 */
     15
     16#include <linux/linkage.h>
     17
     18#include <asm/cacheasm.h>
     19#include <asm/initialize_mmu.h>
     20#include <asm/mxregs.h>
     21#include <asm/regs.h>
     22
     23
     24	.section .SecondaryResetVector.text, "ax"
     25
     26
     27ENTRY(_SecondaryResetVector)
     28	_j _SetupOCD
     29
     30	.begin  no-absolute-literals
     31	.literal_position
     32
     33_SetupOCD:
     34	/*
     35	 * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
     36	 * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
     37	 * xt-gdb to single step via DEBUG exceptions received directly
     38	 * by ocd.
     39	 */
     40#if XCHAL_HAVE_WINDOWED
     41	movi	a1, 1
     42	movi	a0, 0
     43	wsr	a1, windowstart
     44	wsr	a0, windowbase
     45	rsync
     46#endif
     47
     48	movi	a1, LOCKLEVEL
     49	wsr	a1, ps
     50	rsync
     51
     52_SetupMMU:
     53#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
     54	initialize_mmu
     55#endif
     56
     57	/*
     58	 * Start Secondary Processors with NULL pointer to boot params.
     59	 */
     60	movi	a2, 0				#  a2 == NULL
     61	movi	a3, _startup
     62	jx	a3
     63
     64	.end    no-absolute-literals