cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mmu.c (3130B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * xtensa mmu stuff
      4 *
      5 * Extracted from init.c
      6 */
      7#include <linux/memblock.h>
      8#include <linux/percpu.h>
      9#include <linux/init.h>
     10#include <linux/string.h>
     11#include <linux/slab.h>
     12#include <linux/cache.h>
     13
     14#include <asm/tlb.h>
     15#include <asm/tlbflush.h>
     16#include <asm/mmu_context.h>
     17#include <asm/page.h>
     18#include <asm/initialize_mmu.h>
     19#include <asm/io.h>
     20
     21DEFINE_PER_CPU(unsigned long, asid_cache) = ASID_USER_FIRST;
     22
     23#if defined(CONFIG_HIGHMEM)
     24static void * __init init_pmd(unsigned long vaddr, unsigned long n_pages)
     25{
     26	pmd_t *pmd = pmd_off_k(vaddr);
     27	pte_t *pte;
     28	unsigned long i;
     29
     30	n_pages = ALIGN(n_pages, PTRS_PER_PTE);
     31
     32	pr_debug("%s: vaddr: 0x%08lx, n_pages: %ld\n",
     33		 __func__, vaddr, n_pages);
     34
     35	pte = memblock_alloc_low(n_pages * sizeof(pte_t), PAGE_SIZE);
     36	if (!pte)
     37		panic("%s: Failed to allocate %lu bytes align=%lx\n",
     38		      __func__, n_pages * sizeof(pte_t), PAGE_SIZE);
     39
     40	for (i = 0; i < n_pages; ++i)
     41		pte_clear(NULL, 0, pte + i);
     42
     43	for (i = 0; i < n_pages; i += PTRS_PER_PTE, ++pmd) {
     44		pte_t *cur_pte = pte + i;
     45
     46		BUG_ON(!pmd_none(*pmd));
     47		set_pmd(pmd, __pmd(((unsigned long)cur_pte) & PAGE_MASK));
     48		BUG_ON(cur_pte != pte_offset_kernel(pmd, 0));
     49		pr_debug("%s: pmd: 0x%p, pte: 0x%p\n",
     50			 __func__, pmd, cur_pte);
     51	}
     52	return pte;
     53}
     54
     55static void __init fixedrange_init(void)
     56{
     57	BUILD_BUG_ON(FIXADDR_START < TLBTEMP_BASE_1 + TLBTEMP_SIZE);
     58	init_pmd(FIXADDR_START, __end_of_fixed_addresses);
     59}
     60#endif
     61
     62void __init paging_init(void)
     63{
     64#ifdef CONFIG_HIGHMEM
     65	fixedrange_init();
     66	pkmap_page_table = init_pmd(PKMAP_BASE, LAST_PKMAP);
     67	kmap_init();
     68#endif
     69}
     70
     71/*
     72 * Flush the mmu and reset associated register to default values.
     73 */
     74void init_mmu(void)
     75{
     76#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
     77	/*
     78	 * Writing zeros to the instruction and data TLBCFG special
     79	 * registers ensure that valid values exist in the register.
     80	 *
     81	 * For existing PGSZID<w> fields, zero selects the first element
     82	 * of the page-size array.  For nonexistent PGSZID<w> fields,
     83	 * zero is the best value to write.  Also, when changing PGSZID<w>
     84	 * fields, the corresponding TLB must be flushed.
     85	 */
     86	set_itlbcfg_register(0);
     87	set_dtlbcfg_register(0);
     88#endif
     89	init_kio();
     90	local_flush_tlb_all();
     91
     92	/* Set rasid register to a known value. */
     93
     94	set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
     95
     96	/* Set PTEVADDR special register to the start of the page
     97	 * table, which is in kernel mappable space (ie. not
     98	 * statically mapped).  This register's value is undefined on
     99	 * reset.
    100	 */
    101	set_ptevaddr_register(XCHAL_PAGE_TABLE_VADDR);
    102}
    103
    104void init_kio(void)
    105{
    106#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_USE_OF)
    107	/*
    108	 * Update the IO area mapping in case xtensa_kio_paddr has changed
    109	 */
    110	write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
    111			XCHAL_KIO_CACHED_VADDR + 6);
    112	write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
    113			XCHAL_KIO_CACHED_VADDR + 6);
    114	write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
    115			XCHAL_KIO_BYPASS_VADDR + 6);
    116	write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
    117			XCHAL_KIO_BYPASS_VADDR + 6);
    118#endif
    119}