cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hardware.h (897B)

      1/*
      2 * platform/hardware.h
      3 *
      4 * This file is subject to the terms and conditions of the GNU General Public
      5 * License.  See the file "COPYING" in the main directory of this archive
      6 * for more details.
      7 *
      8 * Copyright (C) 2001 Tensilica Inc.
      9 */
     10
     11/*
     12 * This file contains the hardware configuration of the XT2000 board.
     13 */
     14
     15#ifndef _XTENSA_XT2000_HARDWARE_H
     16#define _XTENSA_XT2000_HARDWARE_H
     17
     18#include <asm/core.h>
     19
     20/*
     21 * On-board components.
     22 */
     23
     24#define SONIC83934_INTNUM	XCHAL_EXTINT3_NUM
     25#define SONIC83934_ADDR		IOADDR(0x0d030000)
     26
     27/*
     28 * V3-PCI
     29 */
     30
     31/* The XT2000 uses the V3 as a cascaded interrupt controller for the PCI bus */
     32
     33#define IRQ_PCI_A		(XCHAL_NUM_INTERRUPTS + 0)
     34#define IRQ_PCI_B		(XCHAL_NUM_INTERRUPTS + 1)
     35#define IRQ_PCI_C		(XCHAL_NUM_INTERRUPTS + 2)
     36
     37/*
     38 * Various other components.
     39 */
     40
     41#define XT2000_LED_ADDR		IOADDR(0x0d040000)
     42
     43#endif /* _XTENSA_XT2000_HARDWARE_H */