cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

intel_pmic_chtcrc.c (1510B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Intel Cherry Trail Crystal Cove PMIC operation region driver
      4 *
      5 * Copyright (C) 2019 Hans de Goede <hdegoede@redhat.com>
      6 */
      7
      8#include <linux/acpi.h>
      9#include <linux/init.h>
     10#include <linux/mfd/intel_soc_pmic.h>
     11#include <linux/platform_device.h>
     12#include <linux/regmap.h>
     13#include "intel_pmic.h"
     14
     15/*
     16 * We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
     17 * code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
     18 * Cove Plus" PMIC and talks about Cherry Trail, so presumably that one
     19 * could be used to get register info for the regulators if we need to
     20 * implement regulator support in the future.
     21 *
     22 * For now the sole purpose of this driver is to make
     23 * intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
     24 * CHT Crystal Cove PMIC.
     25 */
     26static const struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = {
     27	.lpat_raw_to_temp = acpi_lpat_raw_to_temp,
     28	.pmic_i2c_address = 0x6e,
     29};
     30
     31static int intel_chtcrc_pmic_opregion_probe(struct platform_device *pdev)
     32{
     33	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
     34	return intel_pmic_install_opregion_handler(&pdev->dev,
     35			ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
     36			&intel_chtcrc_pmic_opregion_data);
     37}
     38
     39static struct platform_driver intel_chtcrc_pmic_opregion_driver = {
     40	.probe = intel_chtcrc_pmic_opregion_probe,
     41	.driver = {
     42		.name = "cht_crystal_cove_pmic",
     43	},
     44};
     45builtin_platform_driver(intel_chtcrc_pmic_opregion_driver);