omap_l3_smx.h (7520B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * OMAP3XXX L3 Interconnect Driver header 4 * 5 * Copyright (C) 2011 Texas Corporation 6 * Felipe Balbi <balbi@ti.com> 7 * Santosh Shilimkar <santosh.shilimkar@ti.com> 8 * sricharan <r.sricharan@ti.com> 9 */ 10#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 11#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 12 13/* Register definitions. All 64-bit wide */ 14#define L3_COMPONENT 0x000 15#define L3_CORE 0x018 16#define L3_AGENT_CONTROL 0x020 17#define L3_AGENT_STATUS 0x028 18#define L3_ERROR_LOG 0x058 19 20#define L3_ERROR_LOG_MULTI (1 << 31) 21#define L3_ERROR_LOG_SECONDARY (1 << 30) 22 23#define L3_ERROR_LOG_ADDR 0x060 24 25/* Register definitions for Sideband Interconnect */ 26#define L3_SI_CONTROL 0x020 27#define L3_SI_FLAG_STATUS_0 0x510 28 29static const u64 shift = 1; 30 31#define L3_STATUS_0_MPUIA_BRST (shift << 0) 32#define L3_STATUS_0_MPUIA_RSP (shift << 1) 33#define L3_STATUS_0_MPUIA_INBAND (shift << 2) 34#define L3_STATUS_0_IVAIA_BRST (shift << 6) 35#define L3_STATUS_0_IVAIA_RSP (shift << 7) 36#define L3_STATUS_0_IVAIA_INBAND (shift << 8) 37#define L3_STATUS_0_SGXIA_BRST (shift << 9) 38#define L3_STATUS_0_SGXIA_RSP (shift << 10) 39#define L3_STATUS_0_SGXIA_MERROR (shift << 11) 40#define L3_STATUS_0_CAMIA_BRST (shift << 12) 41#define L3_STATUS_0_CAMIA_RSP (shift << 13) 42#define L3_STATUS_0_CAMIA_INBAND (shift << 14) 43#define L3_STATUS_0_DISPIA_BRST (shift << 15) 44#define L3_STATUS_0_DISPIA_RSP (shift << 16) 45#define L3_STATUS_0_DMARDIA_BRST (shift << 18) 46#define L3_STATUS_0_DMARDIA_RSP (shift << 19) 47#define L3_STATUS_0_DMAWRIA_BRST (shift << 21) 48#define L3_STATUS_0_DMAWRIA_RSP (shift << 22) 49#define L3_STATUS_0_USBOTGIA_BRST (shift << 24) 50#define L3_STATUS_0_USBOTGIA_RSP (shift << 25) 51#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26) 52#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27) 53#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28) 54#define L3_STATUS_0_SMSTA_REQ (shift << 48) 55#define L3_STATUS_0_GPMCTA_REQ (shift << 49) 56#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50) 57#define L3_STATUS_0_OCMROMTA_REQ (shift << 51) 58#define L3_STATUS_0_IVATA_REQ (shift << 54) 59#define L3_STATUS_0_SGXTA_REQ (shift << 55) 60#define L3_STATUS_0_SGXTA_SERROR (shift << 56) 61#define L3_STATUS_0_GPMCTA_SERROR (shift << 57) 62#define L3_STATUS_0_L4CORETA_REQ (shift << 58) 63#define L3_STATUS_0_L4PERTA_REQ (shift << 59) 64#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) 65#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) 66 67#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ 68 | L3_STATUS_0_MPUIA_RSP \ 69 | L3_STATUS_0_IVAIA_BRST \ 70 | L3_STATUS_0_IVAIA_RSP \ 71 | L3_STATUS_0_SGXIA_BRST \ 72 | L3_STATUS_0_SGXIA_RSP \ 73 | L3_STATUS_0_CAMIA_BRST \ 74 | L3_STATUS_0_CAMIA_RSP \ 75 | L3_STATUS_0_DISPIA_BRST \ 76 | L3_STATUS_0_DISPIA_RSP \ 77 | L3_STATUS_0_DMARDIA_BRST \ 78 | L3_STATUS_0_DMARDIA_RSP \ 79 | L3_STATUS_0_DMAWRIA_BRST \ 80 | L3_STATUS_0_DMAWRIA_RSP \ 81 | L3_STATUS_0_USBOTGIA_BRST \ 82 | L3_STATUS_0_USBOTGIA_RSP \ 83 | L3_STATUS_0_USBHOSTIA_BRST \ 84 | L3_STATUS_0_SMSTA_REQ \ 85 | L3_STATUS_0_GPMCTA_REQ \ 86 | L3_STATUS_0_OCMRAMTA_REQ \ 87 | L3_STATUS_0_OCMROMTA_REQ \ 88 | L3_STATUS_0_IVATA_REQ \ 89 | L3_STATUS_0_SGXTA_REQ \ 90 | L3_STATUS_0_L4CORETA_REQ \ 91 | L3_STATUS_0_L4PERTA_REQ \ 92 | L3_STATUS_0_L4EMUTA_REQ \ 93 | L3_STATUS_0_MAD2DTA_REQ) 94 95#define L3_SI_FLAG_STATUS_1 0x530 96 97#define L3_STATUS_1_MPU_DATAIA (1 << 0) 98#define L3_STATUS_1_DAPIA0 (1 << 3) 99#define L3_STATUS_1_DAPIA1 (1 << 4) 100#define L3_STATUS_1_IVAIA (1 << 6) 101 102#define L3_PM_ERROR_LOG 0x020 103#define L3_PM_CONTROL 0x028 104#define L3_PM_ERROR_CLEAR_SINGLE 0x030 105#define L3_PM_ERROR_CLEAR_MULTI 0x038 106#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n)) 107#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n)) 108#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n)) 109#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n)) 110 111/* L3 error log bit fields. Common for IA and TA */ 112#define L3_ERROR_LOG_CODE 24 113#define L3_ERROR_LOG_INITID 8 114#define L3_ERROR_LOG_CMD 0 115 116/* L3 agent status bit fields. */ 117#define L3_AGENT_STATUS_CLEAR_IA 0x10000000 118#define L3_AGENT_STATUS_CLEAR_TA 0x01000000 119 120#define OMAP34xx_IRQ_L3_APP 10 121#define L3_APPLICATION_ERROR 0x0 122#define L3_DEBUG_ERROR 0x1 123 124enum omap3_l3_initiator_id { 125 /* LCD has 1 ID */ 126 OMAP_L3_LCD = 29, 127 /* SAD2D has 1 ID */ 128 OMAP_L3_SAD2D = 28, 129 /* MPU has 5 IDs */ 130 OMAP_L3_IA_MPU_SS_1 = 27, 131 OMAP_L3_IA_MPU_SS_2 = 26, 132 OMAP_L3_IA_MPU_SS_3 = 25, 133 OMAP_L3_IA_MPU_SS_4 = 24, 134 OMAP_L3_IA_MPU_SS_5 = 23, 135 /* IVA2.2 SS has 3 IDs*/ 136 OMAP_L3_IA_IVA_SS_1 = 22, 137 OMAP_L3_IA_IVA_SS_2 = 21, 138 OMAP_L3_IA_IVA_SS_3 = 20, 139 /* IVA 2.2 SS DMA has 6 IDS */ 140 OMAP_L3_IA_IVA_SS_DMA_1 = 19, 141 OMAP_L3_IA_IVA_SS_DMA_2 = 18, 142 OMAP_L3_IA_IVA_SS_DMA_3 = 17, 143 OMAP_L3_IA_IVA_SS_DMA_4 = 16, 144 OMAP_L3_IA_IVA_SS_DMA_5 = 15, 145 OMAP_L3_IA_IVA_SS_DMA_6 = 14, 146 /* SGX has 1 ID */ 147 OMAP_L3_IA_SGX = 13, 148 /* CAM has 3 ID */ 149 OMAP_L3_IA_CAM_1 = 12, 150 OMAP_L3_IA_CAM_2 = 11, 151 OMAP_L3_IA_CAM_3 = 10, 152 /* DAP has 1 ID */ 153 OMAP_L3_IA_DAP = 9, 154 /* SDMA WR has 2 IDs */ 155 OMAP_L3_SDMA_WR_1 = 8, 156 OMAP_L3_SDMA_WR_2 = 7, 157 /* SDMA RD has 4 IDs */ 158 OMAP_L3_SDMA_RD_1 = 6, 159 OMAP_L3_SDMA_RD_2 = 5, 160 OMAP_L3_SDMA_RD_3 = 4, 161 OMAP_L3_SDMA_RD_4 = 3, 162 /* HSUSB OTG has 1 ID */ 163 OMAP_L3_USBOTG = 2, 164 /* HSUSB HOST has 1 ID */ 165 OMAP_L3_USBHOST = 1, 166}; 167 168enum omap3_l3_code { 169 OMAP_L3_CODE_NOERROR = 0, 170 OMAP_L3_CODE_UNSUP_CMD = 1, 171 OMAP_L3_CODE_ADDR_HOLE = 2, 172 OMAP_L3_CODE_PROTECT_VIOLATION = 3, 173 OMAP_L3_CODE_IN_BAND_ERR = 4, 174 /* codes 5 and 6 are reserved */ 175 OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7, 176 OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8, 177 /* codes 9 - 15 are also reserved */ 178}; 179 180struct omap3_l3 { 181 struct device *dev; 182 struct clk *ick; 183 184 /* memory base*/ 185 void __iomem *rt; 186 187 int debug_irq; 188 int app_irq; 189 190 /* true when and inband functional error occurs */ 191 unsigned inband:1; 192}; 193 194/* offsets for l3 agents in order with the Flag status register */ 195static unsigned int omap3_l3_app_bases[] = { 196 /* MPU IA */ 197 0x1400, 198 0x1400, 199 0x1400, 200 /* RESERVED */ 201 0, 202 0, 203 0, 204 /* IVA 2.2 IA */ 205 0x1800, 206 0x1800, 207 0x1800, 208 /* SGX IA */ 209 0x1c00, 210 0x1c00, 211 /* RESERVED */ 212 0, 213 /* CAMERA IA */ 214 0x5800, 215 0x5800, 216 0x5800, 217 /* DISPLAY IA */ 218 0x5400, 219 0x5400, 220 /* RESERVED */ 221 0, 222 /*SDMA RD IA */ 223 0x4c00, 224 0x4c00, 225 /* RESERVED */ 226 0, 227 /* SDMA WR IA */ 228 0x5000, 229 0x5000, 230 /* RESERVED */ 231 0, 232 /* USB OTG IA */ 233 0x4400, 234 0x4400, 235 0x4400, 236 /* USB HOST IA */ 237 0x4000, 238 0x4000, 239 /* RESERVED */ 240 0, 241 0, 242 0, 243 0, 244 /* SAD2D IA */ 245 0x3000, 246 0x3000, 247 0x3000, 248 /* RESERVED */ 249 0, 250 0, 251 0, 252 0, 253 0, 254 0, 255 0, 256 0, 257 0, 258 0, 259 0, 260 0, 261 /* SMA TA */ 262 0x2000, 263 /* GPMC TA */ 264 0x2400, 265 /* OCM RAM TA */ 266 0x2800, 267 /* OCM ROM TA */ 268 0x2C00, 269 /* L4 CORE TA */ 270 0x6800, 271 /* L4 PER TA */ 272 0x6c00, 273 /* IVA 2.2 TA */ 274 0x6000, 275 /* SGX TA */ 276 0x6400, 277 /* L4 EMU TA */ 278 0x7000, 279 /* GPMC TA */ 280 0x2400, 281 /* L4 CORE TA */ 282 0x6800, 283 /* L4 PER TA */ 284 0x6c00, 285 /* L4 EMU TA */ 286 0x7000, 287 /* MAD2D TA */ 288 0x3400, 289 /* RESERVED */ 290 0, 291 0, 292}; 293 294static unsigned int omap3_l3_debug_bases[] = { 295 /* MPU DATA IA */ 296 0x1400, 297 /* RESERVED */ 298 0, 299 0, 300 /* DAP IA */ 301 0x5c00, 302 0x5c00, 303 /* RESERVED */ 304 0, 305 /* IVA 2.2 IA */ 306 0x1800, 307 /* REST RESERVED */ 308}; 309 310static u32 *omap3_l3_bases[] = { 311 omap3_l3_app_bases, 312 omap3_l3_debug_bases, 313}; 314 315/* 316 * REVISIT define __raw_readll/__raw_writell here, but move them to 317 * <asm/io.h> at some point 318 */ 319#define __raw_writell(v, a) (__chk_io_ptr(a), \ 320 *(volatile u64 __force *)(a) = (v)) 321#define __raw_readll(a) (__chk_io_ptr(a), \ 322 *(volatile u64 __force *)(a)) 323 324#endif