cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tp3780i.h (4388B)

      1/*
      2*
      3* tp3780i.h -- declarations for tp3780i.c
      4*
      5*
      6* Written By: Mike Sullivan IBM Corporation
      7*
      8* Copyright (C) 1999 IBM Corporation
      9*
     10* This program is free software; you can redistribute it and/or modify
     11* it under the terms of the GNU General Public License as published by
     12* the Free Software Foundation; either version 2 of the License, or
     13* (at your option) any later version.
     14*
     15* This program is distributed in the hope that it will be useful,
     16* but WITHOUT ANY WARRANTY; without even the implied warranty of
     17* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     18* GNU General Public License for more details.
     19*
     20* NO WARRANTY
     21* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
     22* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
     23* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
     24* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
     25* solely responsible for determining the appropriateness of using and
     26* distributing the Program and assumes all risks associated with its
     27* exercise of rights under this Agreement, including but not limited to
     28* the risks and costs of program errors, damage to or loss of data,
     29* programs or equipment, and unavailability or interruption of operations.
     30*
     31* DISCLAIMER OF LIABILITY
     32* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
     33* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     34* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
     35* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
     36* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
     37* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
     38* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
     39*
     40* You should have received a copy of the GNU General Public License
     41* along with this program; if not, write to the Free Software
     42* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
     43*
     44*
     45* 10/23/2000 - Alpha Release
     46*	First release to the public
     47*/
     48
     49#ifndef _LINUX_TP3780I_H
     50#define _LINUX_TP3780I_H
     51
     52#include <asm/io.h>
     53#include "mwavepub.h"
     54
     55
     56/* DSP abilities constants for 3780i based Thinkpads */
     57#define TP_ABILITIES_INTS_PER_SEC       39160800
     58#define TP_ABILITIES_DATA_SIZE          32768
     59#define TP_ABILITIES_INST_SIZE          32768
     60#define TP_ABILITIES_MWAVEOS_NAME       "mwaveos0700.dsp"
     61#define TP_ABILITIES_BIOSTASK_NAME      "mwbio701.dsp"
     62
     63
     64/* DSP configuration values for 3780i based Thinkpads */
     65#define TP_CFG_NumTransfers     3	/* 16 transfers */
     66#define TP_CFG_RerequestTimer   1	/* 2 usec */
     67#define TP_CFG_MEMCS16          0	/* Disabled, 16-bit memory assumed */
     68#define TP_CFG_IsaMemCmdWidth   3	/* 295 nsec (16-bit) */
     69#define TP_CFG_GateIOCHRDY      0	/* No IOCHRDY gating */
     70#define TP_CFG_EnablePwrMgmt    1	/* Enable low poser suspend/resume */
     71#define TP_CFG_HBusTimerValue 255	/* HBus timer load value */
     72#define TP_CFG_DisableLBusTimeout 0	/* Enable LBus timeout */
     73#define TP_CFG_N_Divisor       32	/* Clock = 39.1608 Mhz */
     74#define TP_CFG_M_Multiplier    37	/* " */
     75#define TP_CFG_PllBypass        0	/* don't bypass */
     76#define TP_CFG_ChipletEnable 0xFFFF	/* Enable all chiplets */
     77
     78typedef struct {
     79	int bDSPEnabled;
     80	int bShareDspIrq;
     81	int bShareUartIrq;
     82	DSP_3780I_CONFIG_SETTINGS rDspSettings;
     83} THINKPAD_BD_DATA;
     84
     85int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData);
     86int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData);
     87int tp3780I_ClaimResources(THINKPAD_BD_DATA * pBDData);
     88int tp3780I_ReleaseResources(THINKPAD_BD_DATA * pBDData);
     89int tp3780I_EnableDSP(THINKPAD_BD_DATA * pBDData);
     90int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData);
     91int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData);
     92int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData);
     93int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities);
     94void tp3780I_Cleanup(THINKPAD_BD_DATA *pBDData);
     95int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode,
     96                               void __user *pvBuffer, unsigned int uCount,
     97                               unsigned long ulDSPAddr);
     98int tp3780I_ReadWriteDspIStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode,
     99                               void __user *pvBuffer, unsigned int uCount,
    100                               unsigned long ulDSPAddr);
    101
    102
    103#endif