cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tpm_tis_spi.h (1191B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) 2015 Infineon Technologies AG
      4 * Copyright (C) 2016 STMicroelectronics SAS
      5 */
      6
      7#ifndef TPM_TIS_SPI_H
      8#define TPM_TIS_SPI_H
      9
     10#include "tpm_tis_core.h"
     11
     12struct tpm_tis_spi_phy {
     13	struct tpm_tis_data priv;
     14	struct spi_device *spi_device;
     15	int (*flow_control)(struct tpm_tis_spi_phy *phy,
     16			     struct spi_transfer *xfer);
     17	struct completion ready;
     18	unsigned long wake_after;
     19
     20	u8 *iobuf;
     21};
     22
     23static inline struct tpm_tis_spi_phy *to_tpm_tis_spi_phy(struct tpm_tis_data *data)
     24{
     25	return container_of(data, struct tpm_tis_spi_phy, priv);
     26}
     27
     28extern int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy,
     29			    int irq, const struct tpm_tis_phy_ops *phy_ops);
     30
     31extern int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
     32				u8 *in, const u8 *out);
     33
     34#ifdef CONFIG_TCG_TIS_SPI_CR50
     35extern int cr50_spi_probe(struct spi_device *spi);
     36#else
     37static inline int cr50_spi_probe(struct spi_device *spi)
     38{
     39	return -ENODEV;
     40}
     41#endif
     42
     43#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_TCG_TIS_SPI_CR50)
     44extern int tpm_tis_spi_resume(struct device *dev);
     45#else
     46#define tpm_tis_spi_resume	NULL
     47#endif
     48
     49#endif