pmc.h (8186B)
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * drivers/clk/at91/pmc.h 4 * 5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 */ 7 8#ifndef __PMC_H_ 9#define __PMC_H_ 10 11#include <linux/io.h> 12#include <linux/irqdomain.h> 13#include <linux/regmap.h> 14#include <linux/spinlock.h> 15 16#include <dt-bindings/clock/at91.h> 17 18extern spinlock_t pmc_pcr_lock; 19 20struct pmc_data { 21 unsigned int ncore; 22 struct clk_hw **chws; 23 unsigned int nsystem; 24 struct clk_hw **shws; 25 unsigned int nperiph; 26 struct clk_hw **phws; 27 unsigned int ngck; 28 struct clk_hw **ghws; 29 unsigned int npck; 30 struct clk_hw **pchws; 31 32 struct clk_hw *hwtable[]; 33}; 34 35struct clk_range { 36 unsigned long min; 37 unsigned long max; 38}; 39 40#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} 41 42struct clk_master_layout { 43 u32 offset; 44 u32 mask; 45 u8 pres_shift; 46}; 47 48extern const struct clk_master_layout at91rm9200_master_layout; 49extern const struct clk_master_layout at91sam9x5_master_layout; 50 51struct clk_master_characteristics { 52 struct clk_range output; 53 u32 divisors[5]; 54 u8 have_div3_pres; 55}; 56 57struct clk_pll_layout { 58 u32 pllr_mask; 59 u32 mul_mask; 60 u32 frac_mask; 61 u32 div_mask; 62 u32 endiv_mask; 63 u8 mul_shift; 64 u8 frac_shift; 65 u8 div_shift; 66 u8 endiv_shift; 67}; 68 69extern const struct clk_pll_layout at91rm9200_pll_layout; 70extern const struct clk_pll_layout at91sam9g45_pll_layout; 71extern const struct clk_pll_layout at91sam9g20_pllb_layout; 72extern const struct clk_pll_layout sama5d3_pll_layout; 73 74struct clk_pll_characteristics { 75 struct clk_range input; 76 int num_output; 77 const struct clk_range *output; 78 u16 *icpll; 79 u8 *out; 80 u8 upll : 1; 81}; 82 83struct clk_programmable_layout { 84 u8 pres_mask; 85 u8 pres_shift; 86 u8 css_mask; 87 u8 have_slck_mck; 88 u8 is_pres_direct; 89}; 90 91extern const struct clk_programmable_layout at91rm9200_programmable_layout; 92extern const struct clk_programmable_layout at91sam9g45_programmable_layout; 93extern const struct clk_programmable_layout at91sam9x5_programmable_layout; 94 95struct clk_pcr_layout { 96 u32 offset; 97 u32 cmd; 98 u32 div_mask; 99 u32 gckcss_mask; 100 u32 pid_mask; 101}; 102 103/** 104 * struct at91_clk_pms - Power management state for AT91 clock 105 * @rate: clock rate 106 * @parent_rate: clock parent rate 107 * @status: clock status (enabled or disabled) 108 * @parent: clock parent index 109 */ 110struct at91_clk_pms { 111 unsigned long rate; 112 unsigned long parent_rate; 113 unsigned int status; 114 unsigned int parent; 115}; 116 117#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 118#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 119 120#define ndck(a, s) (a[s - 1].id + 1) 121#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) 122struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, 123 unsigned int nperiph, unsigned int ngck, 124 unsigned int npck); 125 126int of_at91_get_clk_range(struct device_node *np, const char *propname, 127 struct clk_range *range); 128 129struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data); 130 131struct clk_hw * __init 132at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, 133 const char *parent_name); 134 135struct clk_hw * __init 136at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, 137 const char *parent_name); 138 139struct clk_hw * __init 140at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, 141 const char *parent_name); 142 143struct clk_hw * __init 144at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 145 const struct clk_pcr_layout *layout, 146 const char *name, const char **parent_names, 147 u32 *mux_table, u8 num_parents, u8 id, 148 const struct clk_range *range, int chg_pid); 149 150struct clk_hw * __init 151at91_clk_register_h32mx(struct regmap *regmap, const char *name, 152 const char *parent_name); 153 154struct clk_hw * __init 155at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, 156 const char * const *parent_names, 157 unsigned int num_parents, u8 bus_id); 158 159struct clk_hw * __init 160at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, 161 u32 frequency, u32 accuracy); 162struct clk_hw * __init 163at91_clk_register_main_osc(struct regmap *regmap, const char *name, 164 const char *parent_name, bool bypass); 165struct clk_hw * __init 166at91_clk_register_rm9200_main(struct regmap *regmap, 167 const char *name, 168 const char *parent_name); 169struct clk_hw * __init 170at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, 171 const char **parent_names, int num_parents); 172 173struct clk_hw * __init 174at91_clk_register_master_pres(struct regmap *regmap, const char *name, 175 int num_parents, const char **parent_names, 176 const struct clk_master_layout *layout, 177 const struct clk_master_characteristics *characteristics, 178 spinlock_t *lock); 179 180struct clk_hw * __init 181at91_clk_register_master_div(struct regmap *regmap, const char *name, 182 const char *parent_names, 183 const struct clk_master_layout *layout, 184 const struct clk_master_characteristics *characteristics, 185 spinlock_t *lock, u32 flags, u32 safe_div); 186 187struct clk_hw * __init 188at91_clk_sama7g5_register_master(struct regmap *regmap, 189 const char *name, int num_parents, 190 const char **parent_names, u32 *mux_table, 191 spinlock_t *lock, u8 id, bool critical, 192 int chg_pid); 193 194struct clk_hw * __init 195at91_clk_register_peripheral(struct regmap *regmap, const char *name, 196 const char *parent_name, u32 id); 197struct clk_hw * __init 198at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, 199 const struct clk_pcr_layout *layout, 200 const char *name, const char *parent_name, 201 u32 id, const struct clk_range *range, 202 int chg_pid); 203 204struct clk_hw * __init 205at91_clk_register_pll(struct regmap *regmap, const char *name, 206 const char *parent_name, u8 id, 207 const struct clk_pll_layout *layout, 208 const struct clk_pll_characteristics *characteristics); 209struct clk_hw * __init 210at91_clk_register_plldiv(struct regmap *regmap, const char *name, 211 const char *parent_name); 212 213struct clk_hw * __init 214sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, 215 const char *name, const char *parent_name, u8 id, 216 const struct clk_pll_characteristics *characteristics, 217 const struct clk_pll_layout *layout, u32 flags, 218 u32 safe_div); 219 220struct clk_hw * __init 221sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, 222 const char *name, const char *parent_name, 223 struct clk_hw *parent_hw, u8 id, 224 const struct clk_pll_characteristics *characteristics, 225 const struct clk_pll_layout *layout, u32 flags); 226 227struct clk_hw * __init 228at91_clk_register_programmable(struct regmap *regmap, const char *name, 229 const char **parent_names, u8 num_parents, u8 id, 230 const struct clk_programmable_layout *layout, 231 u32 *mux_table); 232 233struct clk_hw * __init 234at91_clk_register_sam9260_slow(struct regmap *regmap, 235 const char *name, 236 const char **parent_names, 237 int num_parents); 238 239struct clk_hw * __init 240at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, 241 const char **parent_names, u8 num_parents); 242 243struct clk_hw * __init 244at91_clk_register_system(struct regmap *regmap, const char *name, 245 const char *parent_name, u8 id); 246 247struct clk_hw * __init 248at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, 249 const char **parent_names, u8 num_parents); 250struct clk_hw * __init 251at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, 252 const char *parent_name); 253struct clk_hw * __init 254sam9x60_clk_register_usb(struct regmap *regmap, const char *name, 255 const char **parent_names, u8 num_parents); 256struct clk_hw * __init 257at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, 258 const char *parent_name, const u32 *divisors); 259 260struct clk_hw * __init 261at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr, 262 const char *name, const char *parent_name); 263 264struct clk_hw * __init 265at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, 266 const char *parent_name); 267 268#endif /* __PMC_H_ */