clk-npcm7xx.c (16370B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Nuvoton NPCM7xx Clock Generator 4 * All the clocks are initialized by the bootloader, so this driver allow only 5 * reading of current settings directly from the hardware. 6 * 7 * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com 8 */ 9 10#include <linux/module.h> 11#include <linux/clk-provider.h> 12#include <linux/io.h> 13#include <linux/kernel.h> 14#include <linux/of.h> 15#include <linux/of_address.h> 16#include <linux/slab.h> 17#include <linux/err.h> 18#include <linux/bitfield.h> 19 20#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> 21 22struct npcm7xx_clk_pll { 23 struct clk_hw hw; 24 void __iomem *pllcon; 25 u8 flags; 26}; 27 28#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw) 29 30#define PLLCON_LOKI BIT(31) 31#define PLLCON_LOKS BIT(30) 32#define PLLCON_FBDV GENMASK(27, 16) 33#define PLLCON_OTDV2 GENMASK(15, 13) 34#define PLLCON_PWDEN BIT(12) 35#define PLLCON_OTDV1 GENMASK(10, 8) 36#define PLLCON_INDV GENMASK(5, 0) 37 38static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw, 39 unsigned long parent_rate) 40{ 41 struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw); 42 unsigned long fbdv, indv, otdv1, otdv2; 43 unsigned int val; 44 u64 ret; 45 46 if (parent_rate == 0) { 47 pr_err("%s: parent rate is zero", __func__); 48 return 0; 49 } 50 51 val = readl_relaxed(pll->pllcon); 52 53 indv = FIELD_GET(PLLCON_INDV, val); 54 fbdv = FIELD_GET(PLLCON_FBDV, val); 55 otdv1 = FIELD_GET(PLLCON_OTDV1, val); 56 otdv2 = FIELD_GET(PLLCON_OTDV2, val); 57 58 ret = (u64)parent_rate * fbdv; 59 do_div(ret, indv * otdv1 * otdv2); 60 61 return ret; 62} 63 64static const struct clk_ops npcm7xx_clk_pll_ops = { 65 .recalc_rate = npcm7xx_clk_pll_recalc_rate, 66}; 67 68static struct clk_hw * 69npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, 70 const char *parent_name, unsigned long flags) 71{ 72 struct npcm7xx_clk_pll *pll; 73 struct clk_init_data init; 74 struct clk_hw *hw; 75 int ret; 76 77 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 78 if (!pll) 79 return ERR_PTR(-ENOMEM); 80 81 pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name); 82 83 init.name = name; 84 init.ops = &npcm7xx_clk_pll_ops; 85 init.parent_names = &parent_name; 86 init.num_parents = 1; 87 init.flags = flags; 88 89 pll->pllcon = pllcon; 90 pll->hw.init = &init; 91 92 hw = &pll->hw; 93 94 ret = clk_hw_register(NULL, hw); 95 if (ret) { 96 kfree(pll); 97 hw = ERR_PTR(ret); 98 } 99 100 return hw; 101} 102 103#define NPCM7XX_CLKEN1 (0x00) 104#define NPCM7XX_CLKEN2 (0x28) 105#define NPCM7XX_CLKEN3 (0x30) 106#define NPCM7XX_CLKSEL (0x04) 107#define NPCM7XX_CLKDIV1 (0x08) 108#define NPCM7XX_CLKDIV2 (0x2C) 109#define NPCM7XX_CLKDIV3 (0x58) 110#define NPCM7XX_PLLCON0 (0x0C) 111#define NPCM7XX_PLLCON1 (0x10) 112#define NPCM7XX_PLLCON2 (0x54) 113#define NPCM7XX_SWRSTR (0x14) 114#define NPCM7XX_IRQWAKECON (0x18) 115#define NPCM7XX_IRQWAKEFLAG (0x1C) 116#define NPCM7XX_IPSRST1 (0x20) 117#define NPCM7XX_IPSRST2 (0x24) 118#define NPCM7XX_IPSRST3 (0x34) 119#define NPCM7XX_WD0RCR (0x38) 120#define NPCM7XX_WD1RCR (0x3C) 121#define NPCM7XX_WD2RCR (0x40) 122#define NPCM7XX_SWRSTC1 (0x44) 123#define NPCM7XX_SWRSTC2 (0x48) 124#define NPCM7XX_SWRSTC3 (0x4C) 125#define NPCM7XX_SWRSTC4 (0x50) 126#define NPCM7XX_CORSTC (0x5C) 127#define NPCM7XX_PLLCONG (0x60) 128#define NPCM7XX_AHBCKFI (0x64) 129#define NPCM7XX_SECCNT (0x68) 130#define NPCM7XX_CNTR25M (0x6C) 131 132struct npcm7xx_clk_gate_data { 133 u32 reg; 134 u8 bit_idx; 135 const char *name; 136 const char *parent_name; 137 unsigned long flags; 138 /* 139 * If this clock is exported via DT, set onecell_idx to constant 140 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 141 * this specific clock. Otherwise, set to -1. 142 */ 143 int onecell_idx; 144}; 145 146struct npcm7xx_clk_mux_data { 147 u8 shift; 148 u8 mask; 149 u32 *table; 150 const char *name; 151 const char * const *parent_names; 152 u8 num_parents; 153 unsigned long flags; 154 /* 155 * If this clock is exported via DT, set onecell_idx to constant 156 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 157 * this specific clock. Otherwise, set to -1. 158 */ 159 int onecell_idx; 160 161}; 162 163struct npcm7xx_clk_div_fixed_data { 164 u8 mult; 165 u8 div; 166 const char *name; 167 const char *parent_name; 168 u8 clk_divider_flags; 169 /* 170 * If this clock is exported via DT, set onecell_idx to constant 171 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 172 * this specific clock. Otherwise, set to -1. 173 */ 174 int onecell_idx; 175}; 176 177 178struct npcm7xx_clk_div_data { 179 u32 reg; 180 u8 shift; 181 u8 width; 182 const char *name; 183 const char *parent_name; 184 u8 clk_divider_flags; 185 unsigned long flags; 186 /* 187 * If this clock is exported via DT, set onecell_idx to constant 188 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 189 * this specific clock. Otherwise, set to -1. 190 */ 191 int onecell_idx; 192}; 193 194struct npcm7xx_clk_pll_data { 195 u32 reg; 196 const char *name; 197 const char *parent_name; 198 unsigned long flags; 199 /* 200 * If this clock is exported via DT, set onecell_idx to constant 201 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for 202 * this specific clock. Otherwise, set to -1. 203 */ 204 int onecell_idx; 205}; 206 207/* 208 * Single copy of strings used to refer to clocks within this driver indexed by 209 * above enum. 210 */ 211#define NPCM7XX_CLK_S_REFCLK "refclk" 212#define NPCM7XX_CLK_S_SYSBYPCK "sysbypck" 213#define NPCM7XX_CLK_S_MCBYPCK "mcbypck" 214#define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck" 215#define NPCM7XX_CLK_S_PLL0 "pll0" 216#define NPCM7XX_CLK_S_PLL1 "pll1" 217#define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2" 218#define NPCM7XX_CLK_S_PLL2 "pll2" 219#define NPCM7XX_CLK_S_PLL_GFX "pll_gfx" 220#define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2" 221#define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel" 222#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" 223#define NPCM7XX_CLK_S_MC_MUX "mc_phy" 224#define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ 225#define NPCM7XX_CLK_S_MC "mc" 226#define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/ 227#define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/ 228#define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux" 229#define NPCM7XX_CLK_S_UART_MUX "uart_mux" 230#define NPCM7XX_CLK_S_TIM_MUX "timer_mux" 231#define NPCM7XX_CLK_S_SD_MUX "sd_mux" 232#define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux" 233#define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux" 234#define NPCM7XX_CLK_S_DVC_MUX "dvc_mux" 235#define NPCM7XX_CLK_S_GFX_MUX "gfx_mux" 236#define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel" 237#define NPCM7XX_CLK_S_SPI0 "spi0" 238#define NPCM7XX_CLK_S_SPI3 "spi3" 239#define NPCM7XX_CLK_S_SPIX "spix" 240#define NPCM7XX_CLK_S_APB1 "apb1" 241#define NPCM7XX_CLK_S_APB2 "apb2" 242#define NPCM7XX_CLK_S_APB3 "apb3" 243#define NPCM7XX_CLK_S_APB4 "apb4" 244#define NPCM7XX_CLK_S_APB5 "apb5" 245#define NPCM7XX_CLK_S_TOCK "tock" 246#define NPCM7XX_CLK_S_CLKOUT "clkout" 247#define NPCM7XX_CLK_S_UART "uart" 248#define NPCM7XX_CLK_S_TIMER "timer" 249#define NPCM7XX_CLK_S_MMC "mmc" 250#define NPCM7XX_CLK_S_SDHC "sdhc" 251#define NPCM7XX_CLK_S_ADC "adc" 252#define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem" 253#define NPCM7XX_CLK_S_USBIF "serial_usbif" 254#define NPCM7XX_CLK_S_USB_HOST "usb_host" 255#define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge" 256#define NPCM7XX_CLK_S_PCI "pci" 257 258static u32 pll_mux_table[] = {0, 1, 2, 3}; 259static const char * const pll_mux_parents[] __initconst = { 260 NPCM7XX_CLK_S_PLL0, 261 NPCM7XX_CLK_S_PLL1_DIV2, 262 NPCM7XX_CLK_S_REFCLK, 263 NPCM7XX_CLK_S_PLL2_DIV2, 264}; 265 266static u32 cpuck_mux_table[] = {0, 1, 2, 3}; 267static const char * const cpuck_mux_parents[] __initconst = { 268 NPCM7XX_CLK_S_PLL0, 269 NPCM7XX_CLK_S_PLL1_DIV2, 270 NPCM7XX_CLK_S_REFCLK, 271 NPCM7XX_CLK_S_SYSBYPCK, 272}; 273 274static u32 pixcksel_mux_table[] = {0, 2}; 275static const char * const pixcksel_mux_parents[] __initconst = { 276 NPCM7XX_CLK_S_PLL_GFX, 277 NPCM7XX_CLK_S_REFCLK, 278}; 279 280static u32 sucksel_mux_table[] = {2, 3}; 281static const char * const sucksel_mux_parents[] __initconst = { 282 NPCM7XX_CLK_S_REFCLK, 283 NPCM7XX_CLK_S_PLL2_DIV2, 284}; 285 286static u32 mccksel_mux_table[] = {0, 2, 3}; 287static const char * const mccksel_mux_parents[] __initconst = { 288 NPCM7XX_CLK_S_PLL1_DIV2, 289 NPCM7XX_CLK_S_REFCLK, 290 NPCM7XX_CLK_S_MCBYPCK, 291}; 292 293static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4}; 294static const char * const clkoutsel_mux_parents[] __initconst = { 295 NPCM7XX_CLK_S_PLL0, 296 NPCM7XX_CLK_S_PLL1_DIV2, 297 NPCM7XX_CLK_S_REFCLK, 298 NPCM7XX_CLK_S_PLL_GFX, // divided by 2 299 NPCM7XX_CLK_S_PLL2_DIV2, 300}; 301 302static u32 gfxmsel_mux_table[] = {2, 3}; 303static const char * const gfxmsel_mux_parents[] __initconst = { 304 NPCM7XX_CLK_S_REFCLK, 305 NPCM7XX_CLK_S_PLL2_DIV2, 306}; 307 308static u32 dvcssel_mux_table[] = {2, 3}; 309static const char * const dvcssel_mux_parents[] __initconst = { 310 NPCM7XX_CLK_S_REFCLK, 311 NPCM7XX_CLK_S_PLL2, 312}; 313 314static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = { 315 {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1}, 316 317 {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1, 318 NPCM7XX_CLK_S_REFCLK, 0, -1}, 319 320 {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2, 321 NPCM7XX_CLK_S_REFCLK, 0, -1}, 322 323 {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX, 324 NPCM7XX_CLK_S_REFCLK, 0, -1}, 325}; 326 327static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = { 328 {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX, 329 cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL, 330 NPCM7XX_CLK_CPU}, 331 332 {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX, 333 pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0, 334 NPCM7XX_CLK_GFX_PIXEL}, 335 336 {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX, 337 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 338 339 {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX, 340 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 341 342 {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX, 343 sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1}, 344 345 {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX, 346 mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1}, 347 348 {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX, 349 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 350 351 {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX, 352 pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, 353 354 {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX, 355 clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1}, 356 357 {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX, 358 gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1}, 359 360 {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX, 361 dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1}, 362}; 363 364/* configurable dividers: */ 365static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = { 366 {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC, 367 NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC}, 368 /*30-28 ADCCKDIV*/ 369 {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB, 370 NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB}, 371 /*27-26 CLK4DIV*/ 372 {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER, 373 NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER}, 374 /*25-21 TIMCKDIV*/ 375 {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART, 376 NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART}, 377 /*20-16 UARTDIV*/ 378 {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC, 379 NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC}, 380 /*15-11 MMCCKDIV*/ 381 {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3, 382 NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3}, 383 /*10-6 AHB3CKDIV*/ 384 {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI, 385 NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI}, 386 /*5-2 PCICKDIV*/ 387 {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI, 388 NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL, 389 NPCM7XX_CLK_AXI},/*0 CLK2DIV*/ 390 391 {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4, 392 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4}, 393 /*31-30 APB4CKDIV*/ 394 {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3, 395 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3}, 396 /*29-28 APB3CKDIV*/ 397 {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2, 398 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2}, 399 /*27-26 APB2CKDIV*/ 400 {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1, 401 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1}, 402 /*25-24 APB1CKDIV*/ 403 {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5, 404 NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5}, 405 /*23-22 APB5CKDIV*/ 406 {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT, 407 NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT}, 408 /*20-16 CLKOUTDIV*/ 409 {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX, 410 NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX}, 411 /*15-13 GFXCKDIV*/ 412 {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE, 413 NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU}, 414 /*12-8 SUCKDIV*/ 415 {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST, 416 NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48}, 417 /*7-4 SU48CKDIV*/ 418 {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC, 419 NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC} 420 ,/*3-0 SD1CKDIV*/ 421 422 {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0, 423 NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0}, 424 /*10-6 SPI0CKDV*/ 425 {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX, 426 NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX}, 427 /*5-1 SPIXCKDV*/ 428 429}; 430 431static DEFINE_SPINLOCK(npcm7xx_clk_lock); 432 433static void __init npcm7xx_clk_init(struct device_node *clk_np) 434{ 435 struct clk_hw_onecell_data *npcm7xx_clk_data; 436 void __iomem *clk_base; 437 struct resource res; 438 struct clk_hw *hw; 439 int ret; 440 int i; 441 442 ret = of_address_to_resource(clk_np, 0, &res); 443 if (ret) { 444 pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, 445 ret); 446 return; 447 } 448 449 clk_base = ioremap(res.start, resource_size(&res)); 450 if (!clk_base) 451 goto npcm7xx_init_error; 452 453 npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws, 454 NPCM7XX_NUM_CLOCKS), GFP_KERNEL); 455 if (!npcm7xx_clk_data) 456 goto npcm7xx_init_np_err; 457 458 npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS; 459 460 for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++) 461 npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 462 463 /* Register plls */ 464 for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) { 465 const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i]; 466 467 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, 468 pll_data->name, pll_data->parent_name, pll_data->flags); 469 if (IS_ERR(hw)) { 470 pr_err("npcm7xx_clk: Can't register pll\n"); 471 goto npcm7xx_init_fail; 472 } 473 474 if (pll_data->onecell_idx >= 0) 475 npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw; 476 } 477 478 /* Register fixed dividers */ 479 hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2, 480 NPCM7XX_CLK_S_PLL1, 0, 1, 2); 481 if (IS_ERR(hw)) { 482 pr_err("npcm7xx_clk: Can't register fixed div\n"); 483 goto npcm7xx_init_fail; 484 } 485 486 hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2, 487 NPCM7XX_CLK_S_PLL2, 0, 1, 2); 488 if (IS_ERR(hw)) { 489 pr_err("npcm7xx_clk: Can't register div2\n"); 490 goto npcm7xx_init_fail; 491 } 492 493 /* Register muxes */ 494 for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) { 495 const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i]; 496 497 hw = clk_hw_register_mux_table(NULL, 498 mux_data->name, 499 mux_data->parent_names, mux_data->num_parents, 500 mux_data->flags, clk_base + NPCM7XX_CLKSEL, 501 mux_data->shift, mux_data->mask, 0, 502 mux_data->table, &npcm7xx_clk_lock); 503 504 if (IS_ERR(hw)) { 505 pr_err("npcm7xx_clk: Can't register mux\n"); 506 goto npcm7xx_init_fail; 507 } 508 509 if (mux_data->onecell_idx >= 0) 510 npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw; 511 } 512 513 /* Register clock dividers specified in npcm7xx_divs */ 514 for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) { 515 const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i]; 516 517 hw = clk_hw_register_divider(NULL, div_data->name, 518 div_data->parent_name, 519 div_data->flags, 520 clk_base + div_data->reg, 521 div_data->shift, div_data->width, 522 div_data->clk_divider_flags, &npcm7xx_clk_lock); 523 if (IS_ERR(hw)) { 524 pr_err("npcm7xx_clk: Can't register div table\n"); 525 goto npcm7xx_init_fail; 526 } 527 528 if (div_data->onecell_idx >= 0) 529 npcm7xx_clk_data->hws[div_data->onecell_idx] = hw; 530 } 531 532 ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, 533 npcm7xx_clk_data); 534 if (ret) 535 pr_err("failed to add DT provider: %d\n", ret); 536 537 of_node_put(clk_np); 538 539 return; 540 541npcm7xx_init_fail: 542 kfree(npcm7xx_clk_data->hws); 543npcm7xx_init_np_err: 544 iounmap(clk_base); 545npcm7xx_init_error: 546 of_node_put(clk_np); 547} 548CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);