psc-dm355.c (3861B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PSC clock descriptions for TI DaVinci DM355 4 * 5 * Copyright (C) 2018 David Lechner <david@lechnology.com> 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/clk/davinci.h> 10#include <linux/clk.h> 11#include <linux/clkdev.h> 12#include <linux/init.h> 13#include <linux/kernel.h> 14#include <linux/types.h> 15 16#include "psc.h" 17 18LPSC_CLKDEV1(vpss_master_clkdev, "master", "vpss"); 19LPSC_CLKDEV1(vpss_slave_clkdev, "slave", "vpss"); 20LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1"); 21LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "dm6441-mmc.1"); 22LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1"); 23LPSC_CLKDEV1(usb_clkdev, "usb", NULL); 24LPSC_CLKDEV1(spi2_clkdev, NULL, "spi_davinci.2"); 25LPSC_CLKDEV1(aemif_clkdev, "aemif", NULL); 26LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "dm6441-mmc.0"); 27LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0"); 28LPSC_CLKDEV1(i2c_clkdev, NULL, "i2c_davinci.1"); 29LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); 30LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1"); 31LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2"); 32LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); 33/* REVISIT: gpio-davinci.c should be modified to drop con_id */ 34LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL); 35LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL); 36LPSC_CLKDEV1(timer2_clkdev, NULL, "davinci-wdt"); 37LPSC_CLKDEV1(vpss_dac_clkdev, "vpss_dac", NULL); 38 39static const struct davinci_lpsc_clk_info dm355_psc_info[] = { 40 LPSC(0, 0, vpss_master, pll1_sysclk4, vpss_master_clkdev, 0), 41 LPSC(1, 0, vpss_slave, pll1_sysclk4, vpss_slave_clkdev, 0), 42 LPSC(5, 0, timer3, pll1_auxclk, NULL, 0), 43 LPSC(6, 0, spi1, pll1_sysclk2, spi1_clkdev, 0), 44 LPSC(7, 0, mmcsd1, pll1_sysclk2, mmcsd1_clkdev, 0), 45 LPSC(8, 0, asp1, pll1_sysclk2, mcbsp1_clkdev, 0), 46 LPSC(9, 0, usb, pll1_sysclk2, usb_clkdev, 0), 47 LPSC(10, 0, pwm3, pll1_auxclk, NULL, 0), 48 LPSC(11, 0, spi2, pll1_sysclk2, spi2_clkdev, 0), 49 LPSC(12, 0, rto, pll1_auxclk, NULL, 0), 50 LPSC(14, 0, aemif, pll1_sysclk2, aemif_clkdev, 0), 51 LPSC(15, 0, mmcsd0, pll1_sysclk2, mmcsd0_clkdev, 0), 52 LPSC(17, 0, asp0, pll1_sysclk2, mcbsp0_clkdev, 0), 53 LPSC(18, 0, i2c, pll1_auxclk, i2c_clkdev, 0), 54 LPSC(19, 0, uart0, pll1_auxclk, uart0_clkdev, 0), 55 LPSC(20, 0, uart1, pll1_auxclk, uart1_clkdev, 0), 56 LPSC(21, 0, uart2, pll1_sysclk2, uart2_clkdev, 0), 57 LPSC(22, 0, spi0, pll1_sysclk2, spi0_clkdev, 0), 58 LPSC(23, 0, pwm0, pll1_auxclk, NULL, 0), 59 LPSC(24, 0, pwm1, pll1_auxclk, NULL, 0), 60 LPSC(25, 0, pwm2, pll1_auxclk, NULL, 0), 61 LPSC(26, 0, gpio, pll1_sysclk2, gpio_clkdev, 0), 62 LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED), 63 LPSC(28, 0, timer1, pll1_auxclk, NULL, 0), 64 /* REVISIT: why can't this be disabled? */ 65 LPSC(29, 0, timer2, pll1_auxclk, timer2_clkdev, LPSC_ALWAYS_ENABLED), 66 LPSC(31, 0, arm, pll1_sysclk1, NULL, LPSC_ALWAYS_ENABLED), 67 LPSC(40, 0, mjcp, pll1_sysclk1, NULL, 0), 68 LPSC(41, 0, vpss_dac, pll1_sysclk3, vpss_dac_clkdev, 0), 69 { } 70}; 71 72int dm355_psc_init(struct device *dev, void __iomem *base) 73{ 74 return davinci_psc_register_clocks(dev, dm355_psc_info, 42, base); 75} 76 77static struct clk_bulk_data dm355_psc_parent_clks[] = { 78 { .id = "pll1_sysclk1" }, 79 { .id = "pll1_sysclk2" }, 80 { .id = "pll1_sysclk3" }, 81 { .id = "pll1_sysclk4" }, 82 { .id = "pll1_auxclk" }, 83}; 84 85const struct davinci_psc_init_data dm355_psc_init_data = { 86 .parent_clks = dm355_psc_parent_clks, 87 .num_parent_clks = ARRAY_SIZE(dm355_psc_parent_clks), 88 .psc_init = &dm355_psc_init, 89};