clk-imx8qm-rsrc.c (2341B)
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019-2021 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/firmware/imx/rsrc.h> 8 9#include "clk-scu.h" 10 11/* Keep sorted in the ascending order */ 12static const u32 imx8qm_clk_scu_rsrc_table[] = { 13 IMX_SC_R_A53, 14 IMX_SC_R_A72, 15 IMX_SC_R_DC_0_VIDEO0, 16 IMX_SC_R_DC_0_VIDEO1, 17 IMX_SC_R_DC_0, 18 IMX_SC_R_DC_0_PLL_0, 19 IMX_SC_R_DC_0_PLL_1, 20 IMX_SC_R_DC_1_VIDEO0, 21 IMX_SC_R_DC_1_VIDEO1, 22 IMX_SC_R_DC_1, 23 IMX_SC_R_DC_1_PLL_0, 24 IMX_SC_R_DC_1_PLL_1, 25 IMX_SC_R_SPI_0, 26 IMX_SC_R_SPI_1, 27 IMX_SC_R_SPI_2, 28 IMX_SC_R_SPI_3, 29 IMX_SC_R_UART_0, 30 IMX_SC_R_UART_1, 31 IMX_SC_R_UART_2, 32 IMX_SC_R_UART_3, 33 IMX_SC_R_UART_4, 34 IMX_SC_R_EMVSIM_0, 35 IMX_SC_R_EMVSIM_1, 36 IMX_SC_R_I2C_0, 37 IMX_SC_R_I2C_1, 38 IMX_SC_R_I2C_2, 39 IMX_SC_R_I2C_3, 40 IMX_SC_R_I2C_4, 41 IMX_SC_R_ADC_0, 42 IMX_SC_R_ADC_1, 43 IMX_SC_R_FTM_0, 44 IMX_SC_R_FTM_1, 45 IMX_SC_R_CAN_0, 46 IMX_SC_R_GPU_0_PID0, 47 IMX_SC_R_GPU_1_PID0, 48 IMX_SC_R_PWM_0, 49 IMX_SC_R_PWM_1, 50 IMX_SC_R_PWM_2, 51 IMX_SC_R_PWM_3, 52 IMX_SC_R_PWM_4, 53 IMX_SC_R_PWM_5, 54 IMX_SC_R_PWM_6, 55 IMX_SC_R_PWM_7, 56 IMX_SC_R_GPT_0, 57 IMX_SC_R_GPT_1, 58 IMX_SC_R_GPT_2, 59 IMX_SC_R_GPT_3, 60 IMX_SC_R_GPT_4, 61 IMX_SC_R_FSPI_0, 62 IMX_SC_R_FSPI_1, 63 IMX_SC_R_SDHC_0, 64 IMX_SC_R_SDHC_1, 65 IMX_SC_R_SDHC_2, 66 IMX_SC_R_ENET_0, 67 IMX_SC_R_ENET_1, 68 IMX_SC_R_MLB_0, 69 IMX_SC_R_USB_2, 70 IMX_SC_R_NAND, 71 IMX_SC_R_LVDS_0, 72 IMX_SC_R_LVDS_0_PWM_0, 73 IMX_SC_R_LVDS_0_I2C_0, 74 IMX_SC_R_LVDS_0_I2C_1, 75 IMX_SC_R_LVDS_1, 76 IMX_SC_R_LVDS_1_PWM_0, 77 IMX_SC_R_LVDS_1_I2C_0, 78 IMX_SC_R_LVDS_1_I2C_1, 79 IMX_SC_R_M4_0_I2C, 80 IMX_SC_R_M4_1_I2C, 81 IMX_SC_R_AUDIO_PLL_0, 82 IMX_SC_R_VPU_UART, 83 IMX_SC_R_VPUCORE, 84 IMX_SC_R_MIPI_0, 85 IMX_SC_R_MIPI_0_PWM_0, 86 IMX_SC_R_MIPI_0_I2C_0, 87 IMX_SC_R_MIPI_0_I2C_1, 88 IMX_SC_R_MIPI_1, 89 IMX_SC_R_MIPI_1_PWM_0, 90 IMX_SC_R_MIPI_1_I2C_0, 91 IMX_SC_R_MIPI_1_I2C_1, 92 IMX_SC_R_CSI_0, 93 IMX_SC_R_CSI_0_PWM_0, 94 IMX_SC_R_CSI_0_I2C_0, 95 IMX_SC_R_CSI_1, 96 IMX_SC_R_CSI_1_PWM_0, 97 IMX_SC_R_CSI_1_I2C_0, 98 IMX_SC_R_HDMI, 99 IMX_SC_R_HDMI_I2S, 100 IMX_SC_R_HDMI_I2C_0, 101 IMX_SC_R_HDMI_PLL_0, 102 IMX_SC_R_HDMI_RX, 103 IMX_SC_R_HDMI_RX_BYPASS, 104 IMX_SC_R_HDMI_RX_I2C_0, 105 IMX_SC_R_AUDIO_PLL_1, 106 IMX_SC_R_AUDIO_CLK_0, 107 IMX_SC_R_AUDIO_CLK_1, 108 IMX_SC_R_HDMI_RX_PWM_0, 109 IMX_SC_R_HDMI_PLL_1, 110 IMX_SC_R_VPU, 111}; 112 113const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = { 114 .rsrc = imx8qm_clk_scu_rsrc_table, 115 .num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table), 116};