cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-mt2712-vdec.c (2014B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (c) 2017 MediaTek Inc.
      4 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
      5 */
      6
      7#include <linux/clk-provider.h>
      8#include <linux/platform_device.h>
      9
     10#include "clk-mtk.h"
     11#include "clk-gate.h"
     12
     13#include <dt-bindings/clock/mt2712-clk.h>
     14
     15static const struct mtk_gate_regs vdec0_cg_regs = {
     16	.set_ofs = 0x0,
     17	.clr_ofs = 0x4,
     18	.sta_ofs = 0x0,
     19};
     20
     21static const struct mtk_gate_regs vdec1_cg_regs = {
     22	.set_ofs = 0x8,
     23	.clr_ofs = 0xc,
     24	.sta_ofs = 0x8,
     25};
     26
     27#define GATE_VDEC0(_id, _name, _parent, _shift) {	\
     28		.id = _id,				\
     29		.name = _name,				\
     30		.parent_name = _parent,			\
     31		.regs = &vdec0_cg_regs,			\
     32		.shift = _shift,			\
     33		.ops = &mtk_clk_gate_ops_setclr_inv,	\
     34	}
     35
     36#define GATE_VDEC1(_id, _name, _parent, _shift) {	\
     37		.id = _id,				\
     38		.name = _name,				\
     39		.parent_name = _parent,			\
     40		.regs = &vdec1_cg_regs,			\
     41		.shift = _shift,			\
     42		.ops = &mtk_clk_gate_ops_setclr_inv,	\
     43	}
     44
     45static const struct mtk_gate vdec_clks[] = {
     46	/* VDEC0 */
     47	GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
     48	/* VDEC1 */
     49	GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
     50	GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
     51};
     52
     53static int clk_mt2712_vdec_probe(struct platform_device *pdev)
     54{
     55	struct clk_hw_onecell_data *clk_data;
     56	int r;
     57	struct device_node *node = pdev->dev.of_node;
     58
     59	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
     60
     61	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
     62			clk_data);
     63
     64	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
     65
     66	if (r != 0)
     67		pr_err("%s(): could not register clock provider: %d\n",
     68			__func__, r);
     69
     70	return r;
     71}
     72
     73static const struct of_device_id of_match_clk_mt2712_vdec[] = {
     74	{ .compatible = "mediatek,mt2712-vdecsys", },
     75	{}
     76};
     77
     78static struct platform_driver clk_mt2712_vdec_drv = {
     79	.probe = clk_mt2712_vdec_probe,
     80	.driver = {
     81		.name = "clk-mt2712-vdec",
     82		.of_match_table = of_match_clk_mt2712_vdec,
     83	},
     84};
     85
     86builtin_platform_driver(clk_mt2712_vdec_drv);