cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-mt6779-mfg.c (1376B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (c) 2019 MediaTek Inc.
      4 * Author: Wendell Lin <wendell.lin@mediatek.com>
      5 */
      6
      7#include <linux/module.h>
      8#include <linux/clk-provider.h>
      9#include <linux/platform_device.h>
     10
     11#include "clk-mtk.h"
     12#include "clk-gate.h"
     13
     14#include <dt-bindings/clock/mt6779-clk.h>
     15
     16static const struct mtk_gate_regs mfg_cg_regs = {
     17	.set_ofs = 0x4,
     18	.clr_ofs = 0x8,
     19	.sta_ofs = 0x0,
     20};
     21
     22#define GATE_MFG(_id, _name, _parent, _shift)			\
     23	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift,	\
     24		&mtk_clk_gate_ops_setclr)
     25
     26static const struct mtk_gate mfg_clks[] = {
     27	GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
     28};
     29
     30static int clk_mt6779_mfg_probe(struct platform_device *pdev)
     31{
     32	struct clk_hw_onecell_data *clk_data;
     33	struct device_node *node = pdev->dev.of_node;
     34
     35	clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
     36
     37	mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
     38			       clk_data);
     39
     40	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
     41}
     42
     43static const struct of_device_id of_match_clk_mt6779_mfg[] = {
     44	{ .compatible = "mediatek,mt6779-mfgcfg", },
     45	{}
     46};
     47
     48static struct platform_driver clk_mt6779_mfg_drv = {
     49	.probe = clk_mt6779_mfg_probe,
     50	.driver = {
     51		.name = "clk-mt6779-mfg",
     52		.of_match_table = of_match_clk_mt6779_mfg,
     53	},
     54};
     55
     56module_platform_driver(clk_mt6779_mfg_drv);
     57MODULE_LICENSE("GPL");