clk-mt6797.c (22973B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2016 MediaTek Inc. 4 * Author: Kevin Chen <kevin-cw.chen@mediatek.com> 5 */ 6 7#include <linux/of.h> 8#include <linux/of_address.h> 9#include <linux/of_device.h> 10#include <linux/platform_device.h> 11 12#include "clk-gate.h" 13#include "clk-mtk.h" 14#include "clk-pll.h" 15 16#include <dt-bindings/clock/mt6797-clk.h> 17 18/* 19 * For some clocks, we don't care what their actual rates are. And these 20 * clocks may change their rate on different products or different scenarios. 21 * So we model these clocks' rate as 0, to denote it's not an actual rate. 22 */ 23 24static DEFINE_SPINLOCK(mt6797_clk_lock); 25 26static const struct mtk_fixed_factor top_fixed_divs[] = { 27 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1), 28 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 29 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 30 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 31 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 32 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 33 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 34 FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3), 35 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 36 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 37 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), 38 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 39 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 40 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 41 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 42 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 43 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 44 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1), 45 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 46 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26), 47 FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1), 48 FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1), 49 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 50 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 51 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 52 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 53 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 54 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2), 55 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4), 56 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8), 57 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 58 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 59 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 60 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 61 FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1), 62 FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3), 63 FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2), 64 FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4), 65 FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8), 66 FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10), 67 FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1), 68 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 69 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 70 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 71 FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2), 72 FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1), 73 FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2), 74 FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4), 75 FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1), 76 FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2), 77 FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1), 78 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 79 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 80 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), 81 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), 82 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16), 83 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 84 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), 85 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4), 86 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8), 87}; 88 89static const char * const axi_parents[] = { 90 "clk26m", 91 "syspll_d7", 92 "ulposc_axi_ck_mux", 93}; 94 95static const char * const ulposc_axi_ck_mux_parents[] = { 96 "syspll1_d4", 97 "ulposc_axi_ck_mux_pre", 98}; 99 100static const char * const ulposc_axi_ck_mux_pre_parents[] = { 101 "ulposc_d2", 102 "ulposc_d3", 103}; 104 105static const char * const ddrphycfg_parents[] = { 106 "clk26m", 107 "syspll3_d2", 108 "syspll2_d4", 109 "syspll1_d8", 110}; 111 112static const char * const mm_parents[] = { 113 "clk26m", 114 "imgpll_ck", 115 "univpll1_d2", 116 "syspll1_d2", 117}; 118 119static const char * const pwm_parents[] = { 120 "clk26m", 121 "univpll2_d4", 122 "ulposc_d2", 123 "ulposc_d3", 124 "ulposc_d8", 125 "ulposc_d10", 126 "ulposc_d4", 127}; 128 129static const char * const vdec_parents[] = { 130 "clk26m", 131 "vdecpll_ck", 132 "imgpll_ck", 133 "syspll_d3", 134 "univpll_d5", 135 "clk26m", 136 "clk26m", 137}; 138 139static const char * const venc_parents[] = { 140 "clk26m", 141 "codecpll_ck", 142 "syspll_d3", 143}; 144 145static const char * const mfg_parents[] = { 146 "clk26m", 147 "mfgpll_ck", 148 "syspll_d3", 149 "univpll_d3", 150}; 151 152static const char * const camtg[] = { 153 "clk26m", 154 "univpll_d26", 155 "univpll2_d2", 156}; 157 158static const char * const uart_parents[] = { 159 "clk26m", 160 "univpll2_d8", 161}; 162 163static const char * const spi_parents[] = { 164 "clk26m", 165 "syspll3_d2", 166 "syspll2_d4", 167 "ulposc_spi_ck_mux", 168}; 169 170static const char * const ulposc_spi_ck_mux_parents[] = { 171 "ulposc_d2", 172 "ulposc_d3", 173}; 174 175static const char * const usb20_parents[] = { 176 "clk26m", 177 "univpll1_d8", 178 "syspll4_d2", 179}; 180 181static const char * const msdc50_0_hclk_parents[] = { 182 "clk26m", 183 "syspll1_d2", 184 "syspll2_d2", 185 "syspll4_d2", 186}; 187 188static const char * const msdc50_0_parents[] = { 189 "clk26m", 190 "msdcpll", 191 "syspll_d3", 192 "univpll1_d4", 193 "syspll2_d2", 194 "syspll_d7", 195 "msdcpll_d2", 196 "univpll1_d2", 197 "univpll_d3", 198}; 199 200static const char * const msdc30_1_parents[] = { 201 "clk26m", 202 "univpll2_d2", 203 "msdcpll_d2", 204 "univpll1_d4", 205 "syspll2_d2", 206 "syspll_d7", 207 "univpll_d7", 208}; 209 210static const char * const msdc30_2_parents[] = { 211 "clk26m", 212 "univpll2_d8", 213 "syspll2_d8", 214 "syspll1_d8", 215 "msdcpll_d8", 216 "syspll3_d4", 217 "univpll_d26", 218}; 219 220static const char * const audio_parents[] = { 221 "clk26m", 222 "syspll3_d4", 223 "syspll4_d4", 224 "syspll1_d16", 225}; 226 227static const char * const aud_intbus_parents[] = { 228 "clk26m", 229 "syspll1_d4", 230 "syspll4_d2", 231}; 232 233static const char * const pmicspi_parents[] = { 234 "clk26m", 235 "univpll_d26", 236 "syspll3_d4", 237 "syspll1_d8", 238 "ulposc_d4", 239 "ulposc_d8", 240 "syspll2_d8", 241}; 242 243static const char * const scp_parents[] = { 244 "clk26m", 245 "syspll_d3", 246 "ulposc_ck", 247 "univpll_d5", 248}; 249 250static const char * const atb_parents[] = { 251 "clk26m", 252 "syspll1_d2", 253 "syspll_d5", 254}; 255 256static const char * const mjc_parents[] = { 257 "clk26m", 258 "imgpll_ck", 259 "univpll_d5", 260 "syspll1_d2", 261}; 262 263static const char * const dpi0_parents[] = { 264 "clk26m", 265 "tvdpll_d2", 266 "tvdpll_d4", 267 "tvdpll_d8", 268 "tvdpll_d16", 269 "clk26m", 270 "clk26m", 271}; 272 273static const char * const aud_1_parents[] = { 274 "clk26m", 275 "apll1_ck", 276}; 277 278static const char * const aud_2_parents[] = { 279 "clk26m", 280 "apll2_ck", 281}; 282 283static const char * const ssusb_top_sys_parents[] = { 284 "clk26m", 285 "univpll3_d2", 286}; 287 288static const char * const spm_parents[] = { 289 "clk26m", 290 "syspll1_d8", 291}; 292 293static const char * const bsi_spi_parents[] = { 294 "clk26m", 295 "syspll_d3_d3", 296 "syspll1_d4", 297 "syspll_d7", 298}; 299 300static const char * const audio_h_parents[] = { 301 "clk26m", 302 "apll2_ck", 303 "apll1_ck", 304 "univpll_d7", 305}; 306 307static const char * const mfg_52m_parents[] = { 308 "clk26m", 309 "univpll2_d8", 310 "univpll2_d4", 311 "univpll2_d4", 312}; 313 314static const char * const anc_md32_parents[] = { 315 "clk26m", 316 "syspll1_d2", 317 "univpll_d5", 318}; 319 320/* 321 * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as 322 * critical as otherwise the system will hang after boot. 323 */ 324static const struct mtk_composite top_muxes[] = { 325 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre", 326 ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1), 327 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux", 328 ulposc_axi_ck_mux_parents, 0x0040, 2, 1), 329 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents, 330 0x0040, 0, 2), 331 MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents, 332 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 333 MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents, 334 0x0040, 24, 2), 335 MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7), 336 MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15), 337 MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23), 338 MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31), 339 MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7), 340 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15), 341 MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23), 342 MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux", 343 ulposc_spi_ck_mux_parents, 0x0060, 18, 1), 344 MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents, 345 0x0060, 24, 2, 31), 346 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel", 347 msdc50_0_hclk_parents, 0x0070, 8, 2), 348 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents, 349 0x0070, 16, 4, 23), 350 MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents, 351 0x0070, 24, 3, 31), 352 MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents, 353 0x0080, 0, 3, 7), 354 MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents, 355 0x0080, 16, 2, 23), 356 MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents, 357 0x0080, 24, 2), 358 MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents, 359 0x0090, 0, 3), 360 MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents, 361 0x0090, 8, 2), 362 MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents, 363 0x0090, 16, 2), 364 MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31), 365 MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7), 366 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents, 367 0x00A0, 16, 1, 23), 368 MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents, 369 0x00A0, 24, 1, 31), 370 MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel", 371 ssusb_top_sys_parents, 0x00B0, 8, 1), 372 MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents, 373 0x00C0, 0, 1), 374 MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents, 375 0x00C0, 8, 2), 376 MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents, 377 0x00C0, 16, 2, 23), 378 MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents, 379 0x00C0, 24, 2, 31), 380 MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents, 381 0x0104, 1, 2), 382}; 383 384static int mtk_topckgen_init(struct platform_device *pdev) 385{ 386 struct clk_hw_onecell_data *clk_data; 387 void __iomem *base; 388 struct device_node *node = pdev->dev.of_node; 389 390 base = devm_platform_ioremap_resource(pdev, 0); 391 if (IS_ERR(base)) 392 return PTR_ERR(base); 393 394 clk_data = mtk_alloc_clk_data(CLK_TOP_NR); 395 396 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), 397 clk_data); 398 399 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, 400 &mt6797_clk_lock, clk_data); 401 402 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 403} 404 405static const struct mtk_gate_regs infra0_cg_regs = { 406 .set_ofs = 0x0080, 407 .clr_ofs = 0x0084, 408 .sta_ofs = 0x0090, 409}; 410 411static const struct mtk_gate_regs infra1_cg_regs = { 412 .set_ofs = 0x0088, 413 .clr_ofs = 0x008c, 414 .sta_ofs = 0x0094, 415}; 416 417static const struct mtk_gate_regs infra2_cg_regs = { 418 .set_ofs = 0x00a8, 419 .clr_ofs = 0x00ac, 420 .sta_ofs = 0x00b0, 421}; 422 423#define GATE_ICG0(_id, _name, _parent, _shift) { \ 424 .id = _id, \ 425 .name = _name, \ 426 .parent_name = _parent, \ 427 .regs = &infra0_cg_regs, \ 428 .shift = _shift, \ 429 .ops = &mtk_clk_gate_ops_setclr, \ 430} 431 432#define GATE_ICG1(_id, _name, _parent, _shift) \ 433 GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0) 434 435#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ 436 .id = _id, \ 437 .name = _name, \ 438 .parent_name = _parent, \ 439 .regs = &infra1_cg_regs, \ 440 .shift = _shift, \ 441 .ops = &mtk_clk_gate_ops_setclr, \ 442 .flags = _flags, \ 443} 444 445#define GATE_ICG2(_id, _name, _parent, _shift) \ 446 GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0) 447 448#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ 449 .id = _id, \ 450 .name = _name, \ 451 .parent_name = _parent, \ 452 .regs = &infra2_cg_regs, \ 453 .shift = _shift, \ 454 .ops = &mtk_clk_gate_ops_setclr, \ 455 .flags = _flags, \ 456} 457 458/* 459 * Clock gates dramc and dramc_b are needed by the DRAM controller. 460 * We mark them as critical as otherwise the system will hang after boot. 461 */ 462static const struct mtk_gate infra_clks[] = { 463 GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0), 464 GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1), 465 GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2), 466 GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3), 467 GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4), 468 GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), 469 GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 470 GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7), 471 GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8), 472 GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), 473 GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 474 GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11), 475 GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12), 476 GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13), 477 GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14), 478 GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), 479 GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16), 480 GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17), 481 GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18), 482 GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19), 483 GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21), 484 GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 485 GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 486 GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 487 GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 488 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27), 489 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28), 490 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29), 491 GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30), 492 GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 493 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0), 494 GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1), 495 GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2), 496 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3), 497 GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4), 498 GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5), 499 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7), 500 GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 501 GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 502 GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), 503 GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 504 GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0", 505 "axi_sel", 12), 506 GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1", 507 "axi_sel", 13), 508 GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16), 509 GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17), 510 GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18), 511 GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), 512 GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22), 513 GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 514 GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 515 GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 516 GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 517 "clk26m", 31, CLK_IS_CRITICAL), 518 GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0), 519 GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1), 520 GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2), 521 GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3), 522 GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4), 523 GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5), 524 GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6), 525 GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7), 526 GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8), 527 GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10), 528 GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", 529 "clk26m", 11, CLK_IS_CRITICAL), 530 GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12), 531 GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13), 532 GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15), 533 GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16), 534 GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17), 535 GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18), 536 GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19), 537 GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20), 538 GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21), 539 GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22), 540 GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23), 541 GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys", 542 "ssusb_top_sys_sel", 24), 543 GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9), 544 GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26), 545 GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top", 546 "clk26m", 27), 547 GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", 548 "axi_sel", 28), 549 GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29), 550 GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30), 551 GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31), 552 GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14), 553}; 554 555static const struct mtk_fixed_factor infra_fixed_divs[] = { 556 FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2), 557}; 558 559static struct clk_hw_onecell_data *infra_clk_data; 560 561static void mtk_infrasys_init_early(struct device_node *node) 562{ 563 int r, i; 564 565 if (!infra_clk_data) { 566 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 567 568 for (i = 0; i < CLK_INFRA_NR; i++) 569 infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 570 } 571 572 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 573 infra_clk_data); 574 575 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 576 infra_clk_data); 577 if (r) 578 pr_err("%s(): could not register clock provider: %d\n", 579 __func__, r); 580} 581 582CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg", 583 mtk_infrasys_init_early); 584 585static int mtk_infrasys_init(struct platform_device *pdev) 586{ 587 int i; 588 struct device_node *node = pdev->dev.of_node; 589 590 if (!infra_clk_data) { 591 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); 592 } else { 593 for (i = 0; i < CLK_INFRA_NR; i++) { 594 if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) 595 infra_clk_data->hws[i] = ERR_PTR(-ENOENT); 596 } 597 } 598 599 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 600 infra_clk_data); 601 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), 602 infra_clk_data); 603 604 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 605 infra_clk_data); 606} 607 608#define MT6797_PLL_FMAX (3000UL * MHZ) 609 610#define CON0_MT6797_RST_BAR BIT(24) 611 612#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 613 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 614 _pcw_shift, _div_table) { \ 615 .id = _id, \ 616 .name = _name, \ 617 .reg = _reg, \ 618 .pwr_reg = _pwr_reg, \ 619 .en_mask = _en_mask, \ 620 .flags = _flags, \ 621 .rst_bar_mask = CON0_MT6797_RST_BAR, \ 622 .fmax = MT6797_PLL_FMAX, \ 623 .pcwbits = _pcwbits, \ 624 .pd_reg = _pd_reg, \ 625 .pd_shift = _pd_shift, \ 626 .tuner_reg = _tuner_reg, \ 627 .pcw_reg = _pcw_reg, \ 628 .pcw_shift = _pcw_shift, \ 629 .div_table = _div_table, \ 630} 631 632#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 633 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 634 _pcw_shift) \ 635 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 636 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 637 NULL) 638 639static const struct mtk_pll_data plls[] = { 640 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO, 641 21, 0x220, 4, 0x0, 0x224, 0), 642 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7, 643 0x230, 4, 0x0, 0x234, 14), 644 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21, 645 0x244, 24, 0x0, 0x244, 0), 646 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21, 647 0x250, 4, 0x0, 0x254, 0), 648 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21, 649 0x260, 4, 0x0, 0x264, 0), 650 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21, 651 0x270, 4, 0x0, 0x274, 0), 652 PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21, 653 0x290, 4, 0x0, 0x294, 0), 654 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21, 655 0x2E4, 4, 0x0, 0x2E8, 0), 656 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31, 657 0x2A0, 4, 0x2A8, 0x2A4, 0), 658 PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31, 659 0x2B4, 4, 0x2BC, 0x2B8, 0), 660}; 661 662static int mtk_apmixedsys_init(struct platform_device *pdev) 663{ 664 struct clk_hw_onecell_data *clk_data; 665 struct device_node *node = pdev->dev.of_node; 666 667 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); 668 if (!clk_data) 669 return -ENOMEM; 670 671 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 672 673 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 674} 675 676static const struct of_device_id of_match_clk_mt6797[] = { 677 { 678 .compatible = "mediatek,mt6797-topckgen", 679 .data = mtk_topckgen_init, 680 }, { 681 .compatible = "mediatek,mt6797-infracfg", 682 .data = mtk_infrasys_init, 683 }, { 684 .compatible = "mediatek,mt6797-apmixedsys", 685 .data = mtk_apmixedsys_init, 686 }, { 687 /* sentinel */ 688 } 689}; 690 691static int clk_mt6797_probe(struct platform_device *pdev) 692{ 693 int (*clk_init)(struct platform_device *); 694 int r; 695 696 clk_init = of_device_get_match_data(&pdev->dev); 697 if (!clk_init) 698 return -EINVAL; 699 700 r = clk_init(pdev); 701 if (r) 702 dev_err(&pdev->dev, 703 "could not register clock provider: %s: %d\n", 704 pdev->name, r); 705 706 return r; 707} 708 709static struct platform_driver clk_mt6797_drv = { 710 .probe = clk_mt6797_probe, 711 .driver = { 712 .name = "clk-mt6797", 713 .of_match_table = of_match_clk_mt6797, 714 }, 715}; 716 717static int __init clk_mt6797_init(void) 718{ 719 return platform_driver_register(&clk_mt6797_drv); 720} 721 722arch_initcall(clk_mt6797_init);