cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-mt8183-ipu_conn.c (3616B)

      1// SPDX-License-Identifier: GPL-2.0
      2//
      3// Copyright (c) 2018 MediaTek Inc.
      4// Author: Weiyi Lu <weiyi.lu@mediatek.com>
      5
      6#include <linux/clk-provider.h>
      7#include <linux/platform_device.h>
      8
      9#include "clk-mtk.h"
     10#include "clk-gate.h"
     11
     12#include <dt-bindings/clock/mt8183-clk.h>
     13
     14static const struct mtk_gate_regs ipu_conn_cg_regs = {
     15	.set_ofs = 0x4,
     16	.clr_ofs = 0x8,
     17	.sta_ofs = 0x0,
     18};
     19
     20static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
     21	.set_ofs = 0x10,
     22	.clr_ofs = 0x10,
     23	.sta_ofs = 0x10,
     24};
     25
     26static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
     27	.set_ofs = 0x18,
     28	.clr_ofs = 0x18,
     29	.sta_ofs = 0x18,
     30};
     31
     32static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
     33	.set_ofs = 0x1c,
     34	.clr_ofs = 0x1c,
     35	.sta_ofs = 0x1c,
     36};
     37
     38static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
     39	.set_ofs = 0x20,
     40	.clr_ofs = 0x20,
     41	.sta_ofs = 0x20,
     42};
     43
     44#define GATE_IPU_CONN(_id, _name, _parent, _shift)			\
     45	GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift,	\
     46		&mtk_clk_gate_ops_setclr)
     47
     48#define GATE_IPU_CONN_APB(_id, _name, _parent, _shift)			\
     49	GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift,	\
     50		&mtk_clk_gate_ops_no_setclr)
     51
     52#define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift)		\
     53	GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift,	\
     54		&mtk_clk_gate_ops_no_setclr_inv)
     55
     56#define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift)		\
     57	GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift,	\
     58		&mtk_clk_gate_ops_no_setclr_inv)
     59
     60#define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift)		\
     61	GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift,	\
     62		&mtk_clk_gate_ops_no_setclr_inv)
     63
     64static const struct mtk_gate ipu_conn_clks[] = {
     65	GATE_IPU_CONN(CLK_IPU_CONN_IPU,
     66		"ipu_conn_ipu", "dsp_sel", 0),
     67	GATE_IPU_CONN(CLK_IPU_CONN_AHB,
     68		"ipu_conn_ahb", "dsp_sel", 1),
     69	GATE_IPU_CONN(CLK_IPU_CONN_AXI,
     70		"ipu_conn_axi", "dsp_sel", 2),
     71	GATE_IPU_CONN(CLK_IPU_CONN_ISP,
     72		"ipu_conn_isp", "dsp_sel", 3),
     73	GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
     74		"ipu_conn_cam_adl", "dsp_sel", 4),
     75	GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
     76		"ipu_conn_img_adl", "dsp_sel", 5),
     77	GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
     78		"ipu_conn_dap_rx", "dsp1_sel", 0),
     79	GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
     80		"ipu_conn_apb2axi", "dsp1_sel", 3),
     81	GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
     82		"ipu_conn_apb2ahb", "dsp1_sel", 20),
     83	GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
     84		"ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
     85	GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
     86		"ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
     87	GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
     88		"ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
     89	GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
     90		"ipu_conn_cab3to3", "dsp1_sel", 0),
     91	GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
     92		"ipu_conn_cab2to1", "dsp1_sel", 14),
     93	GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
     94		"ipu_conn_cab3to1_slice", "dsp1_sel", 17),
     95};
     96
     97static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
     98{
     99	struct clk_hw_onecell_data *clk_data;
    100	struct device_node *node = pdev->dev.of_node;
    101
    102	clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
    103
    104	mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
    105			clk_data);
    106
    107	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
    108}
    109
    110static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
    111	{ .compatible = "mediatek,mt8183-ipu_conn", },
    112	{}
    113};
    114
    115static struct platform_driver clk_mt8183_ipu_conn_drv = {
    116	.probe = clk_mt8183_ipu_conn_probe,
    117	.driver = {
    118		.name = "clk-mt8183-ipu_conn",
    119		.of_match_table = of_match_clk_mt8183_ipu_conn,
    120	},
    121};
    122
    123builtin_platform_driver(clk_mt8183_ipu_conn_drv);