cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-mt8186-mdp.c (2708B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2//
      3// Copyright (c) 2022 MediaTek Inc.
      4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
      5
      6#include <linux/clk-provider.h>
      7#include <linux/platform_device.h>
      8#include <dt-bindings/clock/mt8186-clk.h>
      9
     10#include "clk-gate.h"
     11#include "clk-mtk.h"
     12
     13static const struct mtk_gate_regs mdp0_cg_regs = {
     14	.set_ofs = 0x104,
     15	.clr_ofs = 0x108,
     16	.sta_ofs = 0x100,
     17};
     18
     19static const struct mtk_gate_regs mdp2_cg_regs = {
     20	.set_ofs = 0x124,
     21	.clr_ofs = 0x128,
     22	.sta_ofs = 0x120,
     23};
     24
     25#define GATE_MDP0(_id, _name, _parent, _shift)			\
     26	GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
     27
     28#define GATE_MDP2(_id, _name, _parent, _shift)			\
     29	GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
     30
     31static const struct mtk_gate mdp_clks[] = {
     32	/* MDP0 */
     33	GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0", "top_mdp", 0),
     34	GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0", "top_mdp", 1),
     35	GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "top_mdp", 2),
     36	GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "top_mdp", 3),
     37	GATE_MDP0(CLK_MDP_DISP_RDMA, "mdp_disp_rdma", "top_mdp", 4),
     38	GATE_MDP0(CLK_MDP_HMS, "mdp_hms", "top_mdp", 5),
     39	GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "top_mdp", 6),
     40	GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "top_mdp", 7),
     41	GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0", "top_mdp", 8),
     42	GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0", "top_mdp", 9),
     43	GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0", "top_mdp", 10),
     44	GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0", "top_mdp", 11),
     45	GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1", "top_mdp", 12),
     46	GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1", "top_mdp", 13),
     47	GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0", "top_mdp", 14),
     48	GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0", "top_mdp", 15),
     49	GATE_MDP0(CLK_MDP_DISP_WDMA, "mdp_disp_wdma", "top_mdp", 16),
     50	GATE_MDP0(CLK_MDP_COLOR, "mdp_color", "top_mdp", 17),
     51	GATE_MDP0(CLK_MDP_IMG_DL_ASYNC2, "mdp_img_dl_async2", "top_mdp", 18),
     52	/* MDP2 */
     53	GATE_MDP2(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_rel0_as0", "top_mdp", 0),
     54	GATE_MDP2(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_rel1_as1", "top_mdp", 8),
     55	GATE_MDP2(CLK_MDP_IMG_DL_RELAY2_ASYNC2, "mdp_img_dl_rel2_as2", "top_mdp", 24),
     56};
     57
     58static const struct mtk_clk_desc mdp_desc = {
     59	.clks = mdp_clks,
     60	.num_clks = ARRAY_SIZE(mdp_clks),
     61};
     62
     63static const struct of_device_id of_match_clk_mt8186_mdp[] = {
     64	{
     65		.compatible = "mediatek,mt8186-mdpsys",
     66		.data = &mdp_desc,
     67	}, {
     68		/* sentinel */
     69	}
     70};
     71
     72static struct platform_driver clk_mt8186_mdp_drv = {
     73	.probe = mtk_clk_simple_probe,
     74	.remove = mtk_clk_simple_remove,
     75	.driver = {
     76		.name = "clk-mt8186-mdp",
     77		.of_match_table = of_match_clk_mt8186_mdp,
     78	},
     79};
     80builtin_platform_driver(clk_mt8186_mdp_drv);