cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

clk-mt8192-msdc.c (2811B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2//
      3// Copyright (c) 2021 MediaTek Inc.
      4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
      5
      6#include <linux/clk-provider.h>
      7#include <linux/of_device.h>
      8#include <linux/platform_device.h>
      9
     10#include "clk-mtk.h"
     11#include "clk-gate.h"
     12
     13#include <dt-bindings/clock/mt8192-clk.h>
     14
     15static const struct mtk_gate_regs msdc_cg_regs = {
     16	.set_ofs = 0xb4,
     17	.clr_ofs = 0xb4,
     18	.sta_ofs = 0xb4,
     19};
     20
     21static const struct mtk_gate_regs msdc_top_cg_regs = {
     22	.set_ofs = 0x0,
     23	.clr_ofs = 0x0,
     24	.sta_ofs = 0x0,
     25};
     26
     27#define GATE_MSDC(_id, _name, _parent, _shift)	\
     28	GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
     29
     30#define GATE_MSDC_TOP(_id, _name, _parent, _shift)	\
     31	GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
     32
     33static const struct mtk_gate msdc_clks[] = {
     34	GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22),
     35};
     36
     37static const struct mtk_gate msdc_top_clks[] = {
     38	GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0),
     39	GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1),
     40	GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p", "infra_msdc1_src", 2),
     41	GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p", "infra_msdc2_src", 3),
     42	GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0", "axi_sel", 4),
     43	GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1", "axi_sel", 5),
     44	GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2", "axi_sel", 6),
     45	GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg", "axi_sel", 7),
     46	GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi", "axi_sel", 8),
     47	GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p", "infra_msdc0", 9),
     48	GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p", "infra_msdc1", 10),
     49	GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p", "infra_msdc2", 11),
     50	GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m", "clk26m", 12),
     51	GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k", "clk32k", 13),
     52	GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14),
     53};
     54
     55static const struct mtk_clk_desc msdc_desc = {
     56	.clks = msdc_clks,
     57	.num_clks = ARRAY_SIZE(msdc_clks),
     58};
     59
     60static const struct mtk_clk_desc msdc_top_desc = {
     61	.clks = msdc_top_clks,
     62	.num_clks = ARRAY_SIZE(msdc_top_clks),
     63};
     64
     65static const struct of_device_id of_match_clk_mt8192_msdc[] = {
     66	{
     67		.compatible = "mediatek,mt8192-msdc",
     68		.data = &msdc_desc,
     69	}, {
     70		.compatible = "mediatek,mt8192-msdc_top",
     71		.data = &msdc_top_desc,
     72	}, {
     73		/* sentinel */
     74	}
     75};
     76
     77static struct platform_driver clk_mt8192_msdc_drv = {
     78	.probe = mtk_clk_simple_probe,
     79	.driver = {
     80		.name = "clk-mt8192-msdc",
     81		.of_match_table = of_match_clk_mt8192_msdc,
     82	},
     83};
     84
     85builtin_platform_driver(clk_mt8192_msdc_drv);