clk-mt8195-apmixedsys.c (6226B)
1// SPDX-License-Identifier: GPL-2.0-only 2// 3// Copyright (c) 2021 MediaTek Inc. 4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6#include "clk-gate.h" 7#include "clk-mtk.h" 8#include "clk-pll.h" 9 10#include <dt-bindings/clock/mt8195-clk.h> 11#include <linux/of_device.h> 12#include <linux/platform_device.h> 13 14static const struct mtk_gate_regs apmixed_cg_regs = { 15 .set_ofs = 0x8, 16 .clr_ofs = 0x8, 17 .sta_ofs = 0x8, 18}; 19 20#define GATE_APMIXED(_id, _name, _parent, _shift) \ 21 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 22 23static const struct mtk_gate apmixed_clks[] = { 24 GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1), 25}; 26 27#define MT8195_PLL_FMAX (3800UL * MHZ) 28#define MT8195_PLL_FMIN (1500UL * MHZ) 29#define MT8195_INTEGER_BITS 8 30 31#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 32 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 33 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 34 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ 35 _en_reg, _pll_en_bit) { \ 36 .id = _id, \ 37 .name = _name, \ 38 .reg = _reg, \ 39 .pwr_reg = _pwr_reg, \ 40 .en_mask = _en_mask, \ 41 .flags = _flags, \ 42 .rst_bar_mask = _rst_bar_mask, \ 43 .fmax = MT8195_PLL_FMAX, \ 44 .fmin = MT8195_PLL_FMIN, \ 45 .pcwbits = _pcwbits, \ 46 .pcwibits = MT8195_INTEGER_BITS, \ 47 .pd_reg = _pd_reg, \ 48 .pd_shift = _pd_shift, \ 49 .tuner_reg = _tuner_reg, \ 50 .tuner_en_reg = _tuner_en_reg, \ 51 .tuner_en_bit = _tuner_en_bit, \ 52 .pcw_reg = _pcw_reg, \ 53 .pcw_shift = _pcw_shift, \ 54 .pcw_chg_reg = _pcw_chg_reg, \ 55 .en_reg = _en_reg, \ 56 .pll_en_bit = _pll_en_bit, \ 57 } 58 59static const struct mtk_pll_data plls[] = { 60 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0, 61 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9), 62 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0, 63 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9), 64 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0, 65 0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9), 66 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0, 67 0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9), 68 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0, 69 0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9), 70 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0, 71 0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9), 72 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000, 73 HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9), 74 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000, 75 HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9), 76 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0, 77 0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9), 78 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0, 79 0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9), 80 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000, 81 HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9), 82 PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0, 83 0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9), 84 PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0, 85 0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9), 86 PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0, 87 0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9), 88 PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0, 89 0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9), 90 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0, 91 0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9), 92 PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0, 93 0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9), 94 PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0, 95 0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9), 96 PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0, 97 0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9), 98 PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0, 99 0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9), 100 PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000, 101 0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9), 102 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0, 103 0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9), 104 PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0, 105 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9), 106}; 107 108static const struct of_device_id of_match_clk_mt8195_apmixed[] = { 109 { .compatible = "mediatek,mt8195-apmixedsys", }, 110 {} 111}; 112 113static int clk_mt8195_apmixed_probe(struct platform_device *pdev) 114{ 115 struct clk_hw_onecell_data *clk_data; 116 struct device_node *node = pdev->dev.of_node; 117 int r; 118 119 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 120 if (!clk_data) 121 return -ENOMEM; 122 123 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 124 if (r) 125 goto free_apmixed_data; 126 127 r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 128 if (r) 129 goto unregister_plls; 130 131 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 132 if (r) 133 goto unregister_gates; 134 135 platform_set_drvdata(pdev, clk_data); 136 137 return r; 138 139unregister_gates: 140 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 141unregister_plls: 142 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 143free_apmixed_data: 144 mtk_free_clk_data(clk_data); 145 return r; 146} 147 148static int clk_mt8195_apmixed_remove(struct platform_device *pdev) 149{ 150 struct device_node *node = pdev->dev.of_node; 151 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); 152 153 of_clk_del_provider(node); 154 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 155 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 156 mtk_free_clk_data(clk_data); 157 158 return 0; 159} 160 161static struct platform_driver clk_mt8195_apmixed_drv = { 162 .probe = clk_mt8195_apmixed_probe, 163 .remove = clk_mt8195_apmixed_remove, 164 .driver = { 165 .name = "clk-mt8195-apmixed", 166 .of_match_table = of_match_clk_mt8195_apmixed, 167 }, 168}; 169builtin_platform_driver(clk_mt8195_apmixed_drv);