clk-ssp.c (1608B)
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2012 DENX Software Engineering, GmbH 4 * 5 * Pulled from code: 6 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 7 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 8 * 9 * Copyright 2008 Embedded Alley Solutions, Inc. 10 * Copyright 2009-2011 Freescale Semiconductor, Inc. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/init.h> 15#include <linux/clk.h> 16#include <linux/module.h> 17#include <linux/device.h> 18#include <linux/io.h> 19#include <linux/spi/mxs-spi.h> 20 21void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate) 22{ 23 unsigned int ssp_clk, ssp_sck; 24 u32 clock_divide, clock_rate; 25 u32 val; 26 27 ssp_clk = clk_get_rate(ssp->clk); 28 29 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { 30 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); 31 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; 32 if (clock_rate <= 255) 33 break; 34 } 35 36 if (clock_divide > 254) { 37 dev_err(ssp->dev, 38 "%s: cannot set clock to %d\n", __func__, rate); 39 return; 40 } 41 42 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); 43 44 val = readl(ssp->base + HW_SSP_TIMING(ssp)); 45 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 46 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); 47 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); 48 writel(val, ssp->base + HW_SSP_TIMING(ssp)); 49 50 ssp->clk_rate = ssp_sck; 51 52 dev_dbg(ssp->dev, 53 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", 54 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); 55} 56EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);