gcc-msm8998.c (85974B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/platform_device.h> 10#include <linux/module.h> 11#include <linux/of.h> 12#include <linux/of_device.h> 13#include <linux/clk-provider.h> 14#include <linux/regmap.h> 15#include <linux/reset-controller.h> 16 17#include <dt-bindings/clock/qcom,gcc-msm8998.h> 18 19#include "common.h" 20#include "clk-regmap.h" 21#include "clk-alpha-pll.h" 22#include "clk-pll.h" 23#include "clk-rcg.h" 24#include "clk-branch.h" 25#include "reset.h" 26#include "gdsc.h" 27 28static struct pll_vco fabia_vco[] = { 29 { 250000000, 2000000000, 0 }, 30 { 125000000, 1000000000, 1 }, 31}; 32 33static struct clk_alpha_pll gpll0 = { 34 .offset = 0x0, 35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 36 .vco_table = fabia_vco, 37 .num_vco = ARRAY_SIZE(fabia_vco), 38 .clkr = { 39 .enable_reg = 0x52000, 40 .enable_mask = BIT(0), 41 .hw.init = &(struct clk_init_data){ 42 .name = "gpll0", 43 .parent_data = (const struct clk_parent_data []) { 44 { .fw_name = "xo" }, 45 }, 46 .num_parents = 1, 47 .ops = &clk_alpha_pll_fixed_fabia_ops, 48 } 49 }, 50}; 51 52static struct clk_alpha_pll_postdiv gpll0_out_even = { 53 .offset = 0x0, 54 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 55 .clkr.hw.init = &(struct clk_init_data){ 56 .name = "gpll0_out_even", 57 .parent_hws = (const struct clk_hw*[]) { 58 &gpll0.clkr.hw, 59 }, 60 .num_parents = 1, 61 .ops = &clk_alpha_pll_postdiv_fabia_ops, 62 }, 63}; 64 65static struct clk_alpha_pll_postdiv gpll0_out_main = { 66 .offset = 0x0, 67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 68 .clkr.hw.init = &(struct clk_init_data){ 69 .name = "gpll0_out_main", 70 .parent_hws = (const struct clk_hw*[]) { 71 &gpll0.clkr.hw, 72 }, 73 .num_parents = 1, 74 .ops = &clk_alpha_pll_postdiv_fabia_ops, 75 }, 76}; 77 78static struct clk_alpha_pll_postdiv gpll0_out_odd = { 79 .offset = 0x0, 80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 81 .clkr.hw.init = &(struct clk_init_data){ 82 .name = "gpll0_out_odd", 83 .parent_hws = (const struct clk_hw*[]) { 84 &gpll0.clkr.hw, 85 }, 86 .num_parents = 1, 87 .ops = &clk_alpha_pll_postdiv_fabia_ops, 88 }, 89}; 90 91static struct clk_alpha_pll_postdiv gpll0_out_test = { 92 .offset = 0x0, 93 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 94 .clkr.hw.init = &(struct clk_init_data){ 95 .name = "gpll0_out_test", 96 .parent_hws = (const struct clk_hw*[]) { 97 &gpll0.clkr.hw, 98 }, 99 .num_parents = 1, 100 .ops = &clk_alpha_pll_postdiv_fabia_ops, 101 }, 102}; 103 104static struct clk_alpha_pll gpll1 = { 105 .offset = 0x1000, 106 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 107 .vco_table = fabia_vco, 108 .num_vco = ARRAY_SIZE(fabia_vco), 109 .clkr = { 110 .enable_reg = 0x52000, 111 .enable_mask = BIT(1), 112 .hw.init = &(struct clk_init_data){ 113 .name = "gpll1", 114 .parent_data = (const struct clk_parent_data []) { 115 { .fw_name = "xo" }, 116 }, 117 .num_parents = 1, 118 .ops = &clk_alpha_pll_fixed_fabia_ops, 119 } 120 }, 121}; 122 123static struct clk_alpha_pll_postdiv gpll1_out_even = { 124 .offset = 0x1000, 125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 126 .clkr.hw.init = &(struct clk_init_data){ 127 .name = "gpll1_out_even", 128 .parent_hws = (const struct clk_hw*[]) { 129 &gpll1.clkr.hw, 130 }, 131 .num_parents = 1, 132 .ops = &clk_alpha_pll_postdiv_fabia_ops, 133 }, 134}; 135 136static struct clk_alpha_pll_postdiv gpll1_out_main = { 137 .offset = 0x1000, 138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 139 .clkr.hw.init = &(struct clk_init_data){ 140 .name = "gpll1_out_main", 141 .parent_hws = (const struct clk_hw*[]) { 142 &gpll1.clkr.hw, 143 }, 144 .num_parents = 1, 145 .ops = &clk_alpha_pll_postdiv_fabia_ops, 146 }, 147}; 148 149static struct clk_alpha_pll_postdiv gpll1_out_odd = { 150 .offset = 0x1000, 151 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 152 .clkr.hw.init = &(struct clk_init_data){ 153 .name = "gpll1_out_odd", 154 .parent_hws = (const struct clk_hw*[]) { 155 &gpll1.clkr.hw, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_postdiv_fabia_ops, 159 }, 160}; 161 162static struct clk_alpha_pll_postdiv gpll1_out_test = { 163 .offset = 0x1000, 164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 165 .clkr.hw.init = &(struct clk_init_data){ 166 .name = "gpll1_out_test", 167 .parent_hws = (const struct clk_hw*[]) { 168 &gpll1.clkr.hw, 169 }, 170 .num_parents = 1, 171 .ops = &clk_alpha_pll_postdiv_fabia_ops, 172 }, 173}; 174 175static struct clk_alpha_pll gpll2 = { 176 .offset = 0x2000, 177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 178 .vco_table = fabia_vco, 179 .num_vco = ARRAY_SIZE(fabia_vco), 180 .clkr = { 181 .enable_reg = 0x52000, 182 .enable_mask = BIT(2), 183 .hw.init = &(struct clk_init_data){ 184 .name = "gpll2", 185 .parent_data = (const struct clk_parent_data []) { 186 { .fw_name = "xo" }, 187 }, 188 .num_parents = 1, 189 .ops = &clk_alpha_pll_fixed_fabia_ops, 190 } 191 }, 192}; 193 194static struct clk_alpha_pll_postdiv gpll2_out_even = { 195 .offset = 0x2000, 196 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 197 .clkr.hw.init = &(struct clk_init_data){ 198 .name = "gpll2_out_even", 199 .parent_hws = (const struct clk_hw*[]) { 200 &gpll2.clkr.hw, 201 }, 202 .num_parents = 1, 203 .ops = &clk_alpha_pll_postdiv_fabia_ops, 204 }, 205}; 206 207static struct clk_alpha_pll_postdiv gpll2_out_main = { 208 .offset = 0x2000, 209 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 210 .clkr.hw.init = &(struct clk_init_data){ 211 .name = "gpll2_out_main", 212 .parent_hws = (const struct clk_hw*[]) { 213 &gpll2.clkr.hw, 214 }, 215 .num_parents = 1, 216 .ops = &clk_alpha_pll_postdiv_fabia_ops, 217 }, 218}; 219 220static struct clk_alpha_pll_postdiv gpll2_out_odd = { 221 .offset = 0x2000, 222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 223 .clkr.hw.init = &(struct clk_init_data){ 224 .name = "gpll2_out_odd", 225 .parent_hws = (const struct clk_hw*[]) { 226 &gpll2.clkr.hw, 227 }, 228 .num_parents = 1, 229 .ops = &clk_alpha_pll_postdiv_fabia_ops, 230 }, 231}; 232 233static struct clk_alpha_pll_postdiv gpll2_out_test = { 234 .offset = 0x2000, 235 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 236 .clkr.hw.init = &(struct clk_init_data){ 237 .name = "gpll2_out_test", 238 .parent_hws = (const struct clk_hw*[]) { 239 &gpll2.clkr.hw, 240 }, 241 .num_parents = 1, 242 .ops = &clk_alpha_pll_postdiv_fabia_ops, 243 }, 244}; 245 246static struct clk_alpha_pll gpll3 = { 247 .offset = 0x3000, 248 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 249 .vco_table = fabia_vco, 250 .num_vco = ARRAY_SIZE(fabia_vco), 251 .clkr = { 252 .enable_reg = 0x52000, 253 .enable_mask = BIT(3), 254 .hw.init = &(struct clk_init_data){ 255 .name = "gpll3", 256 .parent_data = (const struct clk_parent_data []) { 257 { .fw_name = "xo" }, 258 }, 259 .num_parents = 1, 260 .ops = &clk_alpha_pll_fixed_fabia_ops, 261 } 262 }, 263}; 264 265static struct clk_alpha_pll_postdiv gpll3_out_even = { 266 .offset = 0x3000, 267 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 268 .clkr.hw.init = &(struct clk_init_data){ 269 .name = "gpll3_out_even", 270 .parent_hws = (const struct clk_hw*[]) { 271 &gpll3.clkr.hw, 272 }, 273 .num_parents = 1, 274 .ops = &clk_alpha_pll_postdiv_fabia_ops, 275 }, 276}; 277 278static struct clk_alpha_pll_postdiv gpll3_out_main = { 279 .offset = 0x3000, 280 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 281 .clkr.hw.init = &(struct clk_init_data){ 282 .name = "gpll3_out_main", 283 .parent_hws = (const struct clk_hw*[]) { 284 &gpll3.clkr.hw, 285 }, 286 .num_parents = 1, 287 .ops = &clk_alpha_pll_postdiv_fabia_ops, 288 }, 289}; 290 291static struct clk_alpha_pll_postdiv gpll3_out_odd = { 292 .offset = 0x3000, 293 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 294 .clkr.hw.init = &(struct clk_init_data){ 295 .name = "gpll3_out_odd", 296 .parent_hws = (const struct clk_hw*[]) { 297 &gpll3.clkr.hw, 298 }, 299 .num_parents = 1, 300 .ops = &clk_alpha_pll_postdiv_fabia_ops, 301 }, 302}; 303 304static struct clk_alpha_pll_postdiv gpll3_out_test = { 305 .offset = 0x3000, 306 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 307 .clkr.hw.init = &(struct clk_init_data){ 308 .name = "gpll3_out_test", 309 .parent_hws = (const struct clk_hw*[]) { 310 &gpll3.clkr.hw, 311 }, 312 .num_parents = 1, 313 .ops = &clk_alpha_pll_postdiv_fabia_ops, 314 }, 315}; 316 317static struct clk_alpha_pll gpll4 = { 318 .offset = 0x77000, 319 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 320 .vco_table = fabia_vco, 321 .num_vco = ARRAY_SIZE(fabia_vco), 322 .clkr = { 323 .enable_reg = 0x52000, 324 .enable_mask = BIT(4), 325 .hw.init = &(struct clk_init_data){ 326 .name = "gpll4", 327 .parent_data = (const struct clk_parent_data []) { 328 { .fw_name = "xo" }, 329 }, 330 .num_parents = 1, 331 .ops = &clk_alpha_pll_fixed_fabia_ops, 332 } 333 }, 334}; 335 336static struct clk_alpha_pll_postdiv gpll4_out_even = { 337 .offset = 0x77000, 338 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 339 .clkr.hw.init = &(struct clk_init_data){ 340 .name = "gpll4_out_even", 341 .parent_hws = (const struct clk_hw*[]) { 342 &gpll4.clkr.hw, 343 }, 344 .num_parents = 1, 345 .ops = &clk_alpha_pll_postdiv_fabia_ops, 346 }, 347}; 348 349static struct clk_alpha_pll_postdiv gpll4_out_main = { 350 .offset = 0x77000, 351 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 352 .clkr.hw.init = &(struct clk_init_data){ 353 .name = "gpll4_out_main", 354 .parent_hws = (const struct clk_hw*[]) { 355 &gpll4.clkr.hw, 356 }, 357 .num_parents = 1, 358 .ops = &clk_alpha_pll_postdiv_fabia_ops, 359 }, 360}; 361 362static struct clk_alpha_pll_postdiv gpll4_out_odd = { 363 .offset = 0x77000, 364 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 365 .clkr.hw.init = &(struct clk_init_data){ 366 .name = "gpll4_out_odd", 367 .parent_hws = (const struct clk_hw*[]) { 368 &gpll4.clkr.hw, 369 }, 370 .num_parents = 1, 371 .ops = &clk_alpha_pll_postdiv_fabia_ops, 372 }, 373}; 374 375static struct clk_alpha_pll_postdiv gpll4_out_test = { 376 .offset = 0x77000, 377 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 378 .clkr.hw.init = &(struct clk_init_data){ 379 .name = "gpll4_out_test", 380 .parent_hws = (const struct clk_hw*[]) { 381 &gpll4.clkr.hw, 382 }, 383 .num_parents = 1, 384 .ops = &clk_alpha_pll_postdiv_fabia_ops, 385 }, 386}; 387 388enum { 389 P_AUD_REF_CLK, 390 P_CORE_BI_PLL_TEST_SE, 391 P_GPLL0_OUT_MAIN, 392 P_GPLL4_OUT_MAIN, 393 P_PLL0_EARLY_DIV_CLK_SRC, 394 P_SLEEP_CLK, 395 P_XO, 396}; 397 398static const struct parent_map gcc_parent_map_0[] = { 399 { P_XO, 0 }, 400 { P_GPLL0_OUT_MAIN, 1 }, 401 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 402 { P_CORE_BI_PLL_TEST_SE, 7 }, 403}; 404 405static const struct clk_parent_data gcc_parent_data_0[] = { 406 { .fw_name = "xo" }, 407 { .hw = &gpll0_out_main.clkr.hw }, 408 { .hw = &gpll0_out_main.clkr.hw }, 409 { .fw_name = "core_bi_pll_test_se" }, 410}; 411 412static const struct parent_map gcc_parent_map_1[] = { 413 { P_XO, 0 }, 414 { P_GPLL0_OUT_MAIN, 1 }, 415 { P_CORE_BI_PLL_TEST_SE, 7 }, 416}; 417 418static const struct clk_parent_data gcc_parent_data_1[] = { 419 { .fw_name = "xo" }, 420 { .hw = &gpll0_out_main.clkr.hw }, 421 { .fw_name = "core_bi_pll_test_se" }, 422}; 423 424static const struct parent_map gcc_parent_map_2[] = { 425 { P_XO, 0 }, 426 { P_GPLL0_OUT_MAIN, 1 }, 427 { P_SLEEP_CLK, 5 }, 428 { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, 429 { P_CORE_BI_PLL_TEST_SE, 7 }, 430}; 431 432static const struct clk_parent_data gcc_parent_data_2[] = { 433 { .fw_name = "xo" }, 434 { .hw = &gpll0_out_main.clkr.hw }, 435 { .fw_name = "sleep_clk" }, 436 { .hw = &gpll0_out_main.clkr.hw }, 437 { .fw_name = "core_bi_pll_test_se" }, 438}; 439 440static const struct parent_map gcc_parent_map_3[] = { 441 { P_XO, 0 }, 442 { P_SLEEP_CLK, 5 }, 443 { P_CORE_BI_PLL_TEST_SE, 7 }, 444}; 445 446static const struct clk_parent_data gcc_parent_data_3[] = { 447 { .fw_name = "xo" }, 448 { .fw_name = "sleep_clk" }, 449 { .fw_name = "core_bi_pll_test_se" }, 450}; 451 452static const struct parent_map gcc_parent_map_4[] = { 453 { P_XO, 0 }, 454 { P_GPLL0_OUT_MAIN, 1 }, 455 { P_GPLL4_OUT_MAIN, 5 }, 456 { P_CORE_BI_PLL_TEST_SE, 7 }, 457}; 458 459static const struct clk_parent_data gcc_parent_data_4[] = { 460 { .fw_name = "xo" }, 461 { .hw = &gpll0_out_main.clkr.hw }, 462 { .hw = &gpll4_out_main.clkr.hw }, 463 { .fw_name = "core_bi_pll_test_se" }, 464}; 465 466static const struct parent_map gcc_parent_map_5[] = { 467 { P_XO, 0 }, 468 { P_GPLL0_OUT_MAIN, 1 }, 469 { P_AUD_REF_CLK, 2 }, 470 { P_CORE_BI_PLL_TEST_SE, 7 }, 471}; 472 473static const struct clk_parent_data gcc_parent_data_5[] = { 474 { .fw_name = "xo" }, 475 { .hw = &gpll0_out_main.clkr.hw }, 476 { .fw_name = "aud_ref_clk" }, 477 { .fw_name = "core_bi_pll_test_se" }, 478}; 479 480static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { 481 F(19200000, P_XO, 1, 0, 0), 482 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 483 { } 484}; 485 486static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 487 .cmd_rcgr = 0x19020, 488 .mnd_width = 0, 489 .hid_width = 5, 490 .parent_map = gcc_parent_map_1, 491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "blsp1_qup1_i2c_apps_clk_src", 494 .parent_data = gcc_parent_data_1, 495 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 496 .ops = &clk_rcg2_ops, 497 }, 498}; 499 500static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { 501 F(960000, P_XO, 10, 1, 2), 502 F(4800000, P_XO, 4, 0, 0), 503 F(9600000, P_XO, 2, 0, 0), 504 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), 505 F(19200000, P_XO, 1, 0, 0), 506 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 507 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 508 { } 509}; 510 511static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 512 .cmd_rcgr = 0x1900c, 513 .mnd_width = 8, 514 .hid_width = 5, 515 .parent_map = gcc_parent_map_0, 516 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 517 .clkr.hw.init = &(struct clk_init_data){ 518 .name = "blsp1_qup1_spi_apps_clk_src", 519 .parent_data = gcc_parent_data_0, 520 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 521 .ops = &clk_rcg2_ops, 522 }, 523}; 524 525static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 526 .cmd_rcgr = 0x1b020, 527 .mnd_width = 0, 528 .hid_width = 5, 529 .parent_map = gcc_parent_map_1, 530 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 531 .clkr.hw.init = &(struct clk_init_data){ 532 .name = "blsp1_qup2_i2c_apps_clk_src", 533 .parent_data = gcc_parent_data_1, 534 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 535 .ops = &clk_rcg2_ops, 536 }, 537}; 538 539static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 540 .cmd_rcgr = 0x1b00c, 541 .mnd_width = 8, 542 .hid_width = 5, 543 .parent_map = gcc_parent_map_0, 544 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 545 .clkr.hw.init = &(struct clk_init_data){ 546 .name = "blsp1_qup2_spi_apps_clk_src", 547 .parent_data = gcc_parent_data_0, 548 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 549 .ops = &clk_rcg2_ops, 550 }, 551}; 552 553static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 554 .cmd_rcgr = 0x1d020, 555 .mnd_width = 0, 556 .hid_width = 5, 557 .parent_map = gcc_parent_map_1, 558 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 559 .clkr.hw.init = &(struct clk_init_data){ 560 .name = "blsp1_qup3_i2c_apps_clk_src", 561 .parent_data = gcc_parent_data_1, 562 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 563 .ops = &clk_rcg2_ops, 564 }, 565}; 566 567static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 568 .cmd_rcgr = 0x1d00c, 569 .mnd_width = 8, 570 .hid_width = 5, 571 .parent_map = gcc_parent_map_0, 572 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 573 .clkr.hw.init = &(struct clk_init_data){ 574 .name = "blsp1_qup3_spi_apps_clk_src", 575 .parent_data = gcc_parent_data_0, 576 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 577 .ops = &clk_rcg2_ops, 578 }, 579}; 580 581static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 582 .cmd_rcgr = 0x1f020, 583 .mnd_width = 0, 584 .hid_width = 5, 585 .parent_map = gcc_parent_map_1, 586 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 587 .clkr.hw.init = &(struct clk_init_data){ 588 .name = "blsp1_qup4_i2c_apps_clk_src", 589 .parent_data = gcc_parent_data_1, 590 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 591 .ops = &clk_rcg2_ops, 592 }, 593}; 594 595static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 596 .cmd_rcgr = 0x1f00c, 597 .mnd_width = 8, 598 .hid_width = 5, 599 .parent_map = gcc_parent_map_0, 600 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 601 .clkr.hw.init = &(struct clk_init_data){ 602 .name = "blsp1_qup4_spi_apps_clk_src", 603 .parent_data = gcc_parent_data_0, 604 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 605 .ops = &clk_rcg2_ops, 606 }, 607}; 608 609static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 610 .cmd_rcgr = 0x21020, 611 .mnd_width = 0, 612 .hid_width = 5, 613 .parent_map = gcc_parent_map_1, 614 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 615 .clkr.hw.init = &(struct clk_init_data){ 616 .name = "blsp1_qup5_i2c_apps_clk_src", 617 .parent_data = gcc_parent_data_1, 618 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 619 .ops = &clk_rcg2_ops, 620 }, 621}; 622 623static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 624 .cmd_rcgr = 0x2100c, 625 .mnd_width = 8, 626 .hid_width = 5, 627 .parent_map = gcc_parent_map_0, 628 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 629 .clkr.hw.init = &(struct clk_init_data){ 630 .name = "blsp1_qup5_spi_apps_clk_src", 631 .parent_data = gcc_parent_data_0, 632 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 633 .ops = &clk_rcg2_ops, 634 }, 635}; 636 637static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 638 .cmd_rcgr = 0x23020, 639 .mnd_width = 0, 640 .hid_width = 5, 641 .parent_map = gcc_parent_map_1, 642 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 643 .clkr.hw.init = &(struct clk_init_data){ 644 .name = "blsp1_qup6_i2c_apps_clk_src", 645 .parent_data = gcc_parent_data_1, 646 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 647 .ops = &clk_rcg2_ops, 648 }, 649}; 650 651static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 652 .cmd_rcgr = 0x2300c, 653 .mnd_width = 8, 654 .hid_width = 5, 655 .parent_map = gcc_parent_map_0, 656 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 657 .clkr.hw.init = &(struct clk_init_data){ 658 .name = "blsp1_qup6_spi_apps_clk_src", 659 .parent_data = gcc_parent_data_0, 660 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 661 .ops = &clk_rcg2_ops, 662 }, 663}; 664 665static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { 666 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), 667 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), 668 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), 669 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), 670 F(19200000, P_XO, 1, 0, 0), 671 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), 672 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), 673 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), 674 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), 675 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), 676 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), 677 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), 678 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), 679 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 680 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), 681 { } 682}; 683 684static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 685 .cmd_rcgr = 0x1a00c, 686 .mnd_width = 16, 687 .hid_width = 5, 688 .parent_map = gcc_parent_map_0, 689 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 690 .clkr.hw.init = &(struct clk_init_data){ 691 .name = "blsp1_uart1_apps_clk_src", 692 .parent_data = gcc_parent_data_0, 693 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 694 .ops = &clk_rcg2_ops, 695 }, 696}; 697 698static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 699 .cmd_rcgr = 0x1c00c, 700 .mnd_width = 16, 701 .hid_width = 5, 702 .parent_map = gcc_parent_map_0, 703 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 704 .clkr.hw.init = &(struct clk_init_data){ 705 .name = "blsp1_uart2_apps_clk_src", 706 .parent_data = gcc_parent_data_0, 707 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 708 .ops = &clk_rcg2_ops, 709 }, 710}; 711 712static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 713 .cmd_rcgr = 0x1e00c, 714 .mnd_width = 16, 715 .hid_width = 5, 716 .parent_map = gcc_parent_map_0, 717 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 718 .clkr.hw.init = &(struct clk_init_data){ 719 .name = "blsp1_uart3_apps_clk_src", 720 .parent_data = gcc_parent_data_0, 721 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 722 .ops = &clk_rcg2_ops, 723 }, 724}; 725 726static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 727 .cmd_rcgr = 0x26020, 728 .mnd_width = 0, 729 .hid_width = 5, 730 .parent_map = gcc_parent_map_1, 731 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 732 .clkr.hw.init = &(struct clk_init_data){ 733 .name = "blsp2_qup1_i2c_apps_clk_src", 734 .parent_data = gcc_parent_data_1, 735 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 736 .ops = &clk_rcg2_ops, 737 }, 738}; 739 740static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 741 .cmd_rcgr = 0x2600c, 742 .mnd_width = 8, 743 .hid_width = 5, 744 .parent_map = gcc_parent_map_0, 745 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 746 .clkr.hw.init = &(struct clk_init_data){ 747 .name = "blsp2_qup1_spi_apps_clk_src", 748 .parent_data = gcc_parent_data_0, 749 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 750 .ops = &clk_rcg2_ops, 751 }, 752}; 753 754static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 755 .cmd_rcgr = 0x28020, 756 .mnd_width = 0, 757 .hid_width = 5, 758 .parent_map = gcc_parent_map_1, 759 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 760 .clkr.hw.init = &(struct clk_init_data){ 761 .name = "blsp2_qup2_i2c_apps_clk_src", 762 .parent_data = gcc_parent_data_1, 763 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 764 .ops = &clk_rcg2_ops, 765 }, 766}; 767 768static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 769 .cmd_rcgr = 0x2800c, 770 .mnd_width = 8, 771 .hid_width = 5, 772 .parent_map = gcc_parent_map_0, 773 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 774 .clkr.hw.init = &(struct clk_init_data){ 775 .name = "blsp2_qup2_spi_apps_clk_src", 776 .parent_data = gcc_parent_data_0, 777 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 778 .ops = &clk_rcg2_ops, 779 }, 780}; 781 782static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 783 .cmd_rcgr = 0x2a020, 784 .mnd_width = 0, 785 .hid_width = 5, 786 .parent_map = gcc_parent_map_1, 787 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 788 .clkr.hw.init = &(struct clk_init_data){ 789 .name = "blsp2_qup3_i2c_apps_clk_src", 790 .parent_data = gcc_parent_data_1, 791 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 792 .ops = &clk_rcg2_ops, 793 }, 794}; 795 796static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 797 .cmd_rcgr = 0x2a00c, 798 .mnd_width = 8, 799 .hid_width = 5, 800 .parent_map = gcc_parent_map_0, 801 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 802 .clkr.hw.init = &(struct clk_init_data){ 803 .name = "blsp2_qup3_spi_apps_clk_src", 804 .parent_data = gcc_parent_data_0, 805 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 806 .ops = &clk_rcg2_ops, 807 }, 808}; 809 810static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 811 .cmd_rcgr = 0x2c020, 812 .mnd_width = 0, 813 .hid_width = 5, 814 .parent_map = gcc_parent_map_1, 815 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 816 .clkr.hw.init = &(struct clk_init_data){ 817 .name = "blsp2_qup4_i2c_apps_clk_src", 818 .parent_data = gcc_parent_data_1, 819 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 820 .ops = &clk_rcg2_ops, 821 }, 822}; 823 824static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 825 .cmd_rcgr = 0x2c00c, 826 .mnd_width = 8, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 830 .clkr.hw.init = &(struct clk_init_data){ 831 .name = "blsp2_qup4_spi_apps_clk_src", 832 .parent_data = gcc_parent_data_0, 833 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 834 .ops = &clk_rcg2_ops, 835 }, 836}; 837 838static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 839 .cmd_rcgr = 0x2e020, 840 .mnd_width = 0, 841 .hid_width = 5, 842 .parent_map = gcc_parent_map_1, 843 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 844 .clkr.hw.init = &(struct clk_init_data){ 845 .name = "blsp2_qup5_i2c_apps_clk_src", 846 .parent_data = gcc_parent_data_1, 847 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 848 .ops = &clk_rcg2_ops, 849 }, 850}; 851 852static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 853 .cmd_rcgr = 0x2e00c, 854 .mnd_width = 8, 855 .hid_width = 5, 856 .parent_map = gcc_parent_map_0, 857 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 858 .clkr.hw.init = &(struct clk_init_data){ 859 .name = "blsp2_qup5_spi_apps_clk_src", 860 .parent_data = gcc_parent_data_0, 861 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 862 .ops = &clk_rcg2_ops, 863 }, 864}; 865 866static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 867 .cmd_rcgr = 0x30020, 868 .mnd_width = 0, 869 .hid_width = 5, 870 .parent_map = gcc_parent_map_1, 871 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, 872 .clkr.hw.init = &(struct clk_init_data){ 873 .name = "blsp2_qup6_i2c_apps_clk_src", 874 .parent_data = gcc_parent_data_1, 875 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 876 .ops = &clk_rcg2_ops, 877 }, 878}; 879 880static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 881 .cmd_rcgr = 0x3000c, 882 .mnd_width = 8, 883 .hid_width = 5, 884 .parent_map = gcc_parent_map_0, 885 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, 886 .clkr.hw.init = &(struct clk_init_data){ 887 .name = "blsp2_qup6_spi_apps_clk_src", 888 .parent_data = gcc_parent_data_0, 889 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 890 .ops = &clk_rcg2_ops, 891 }, 892}; 893 894static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 895 .cmd_rcgr = 0x2700c, 896 .mnd_width = 16, 897 .hid_width = 5, 898 .parent_map = gcc_parent_map_0, 899 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 900 .clkr.hw.init = &(struct clk_init_data){ 901 .name = "blsp2_uart1_apps_clk_src", 902 .parent_data = gcc_parent_data_0, 903 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 904 .ops = &clk_rcg2_ops, 905 }, 906}; 907 908static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 909 .cmd_rcgr = 0x2900c, 910 .mnd_width = 16, 911 .hid_width = 5, 912 .parent_map = gcc_parent_map_0, 913 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 914 .clkr.hw.init = &(struct clk_init_data){ 915 .name = "blsp2_uart2_apps_clk_src", 916 .parent_data = gcc_parent_data_0, 917 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 918 .ops = &clk_rcg2_ops, 919 }, 920}; 921 922static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 923 .cmd_rcgr = 0x2b00c, 924 .mnd_width = 16, 925 .hid_width = 5, 926 .parent_map = gcc_parent_map_0, 927 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, 928 .clkr.hw.init = &(struct clk_init_data){ 929 .name = "blsp2_uart3_apps_clk_src", 930 .parent_data = gcc_parent_data_0, 931 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 932 .ops = &clk_rcg2_ops, 933 }, 934}; 935 936static const struct freq_tbl ftbl_gp1_clk_src[] = { 937 F(19200000, P_XO, 1, 0, 0), 938 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 939 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 940 { } 941}; 942 943static struct clk_rcg2 gp1_clk_src = { 944 .cmd_rcgr = 0x64004, 945 .mnd_width = 8, 946 .hid_width = 5, 947 .parent_map = gcc_parent_map_2, 948 .freq_tbl = ftbl_gp1_clk_src, 949 .clkr.hw.init = &(struct clk_init_data){ 950 .name = "gp1_clk_src", 951 .parent_data = gcc_parent_data_2, 952 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 953 .ops = &clk_rcg2_ops, 954 }, 955}; 956 957static struct clk_rcg2 gp2_clk_src = { 958 .cmd_rcgr = 0x65004, 959 .mnd_width = 8, 960 .hid_width = 5, 961 .parent_map = gcc_parent_map_2, 962 .freq_tbl = ftbl_gp1_clk_src, 963 .clkr.hw.init = &(struct clk_init_data){ 964 .name = "gp2_clk_src", 965 .parent_data = gcc_parent_data_2, 966 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 967 .ops = &clk_rcg2_ops, 968 }, 969}; 970 971static struct clk_rcg2 gp3_clk_src = { 972 .cmd_rcgr = 0x66004, 973 .mnd_width = 8, 974 .hid_width = 5, 975 .parent_map = gcc_parent_map_2, 976 .freq_tbl = ftbl_gp1_clk_src, 977 .clkr.hw.init = &(struct clk_init_data){ 978 .name = "gp3_clk_src", 979 .parent_data = gcc_parent_data_2, 980 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 981 .ops = &clk_rcg2_ops, 982 }, 983}; 984 985static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { 986 F(19200000, P_XO, 1, 0, 0), 987 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 988 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 989 { } 990}; 991 992static struct clk_rcg2 hmss_ahb_clk_src = { 993 .cmd_rcgr = 0x48014, 994 .mnd_width = 0, 995 .hid_width = 5, 996 .parent_map = gcc_parent_map_1, 997 .freq_tbl = ftbl_hmss_ahb_clk_src, 998 .clkr.hw.init = &(struct clk_init_data){ 999 .name = "hmss_ahb_clk_src", 1000 .parent_data = gcc_parent_data_1, 1001 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1002 .ops = &clk_rcg2_ops, 1003 }, 1004}; 1005 1006static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { 1007 F(19200000, P_XO, 1, 0, 0), 1008 { } 1009}; 1010 1011static struct clk_rcg2 hmss_rbcpr_clk_src = { 1012 .cmd_rcgr = 0x48044, 1013 .mnd_width = 0, 1014 .hid_width = 5, 1015 .parent_map = gcc_parent_map_1, 1016 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1017 .clkr.hw.init = &(struct clk_init_data){ 1018 .name = "hmss_rbcpr_clk_src", 1019 .parent_data = gcc_parent_data_1, 1020 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1021 .ops = &clk_rcg2_ops, 1022 }, 1023}; 1024 1025static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { 1026 F(1010526, P_XO, 1, 1, 19), 1027 { } 1028}; 1029 1030static struct clk_rcg2 pcie_aux_clk_src = { 1031 .cmd_rcgr = 0x6c000, 1032 .mnd_width = 16, 1033 .hid_width = 5, 1034 .parent_map = gcc_parent_map_3, 1035 .freq_tbl = ftbl_pcie_aux_clk_src, 1036 .clkr.hw.init = &(struct clk_init_data){ 1037 .name = "pcie_aux_clk_src", 1038 .parent_data = gcc_parent_data_3, 1039 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1040 .ops = &clk_rcg2_ops, 1041 }, 1042}; 1043 1044static const struct freq_tbl ftbl_pdm2_clk_src[] = { 1045 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1046 { } 1047}; 1048 1049static struct clk_rcg2 pdm2_clk_src = { 1050 .cmd_rcgr = 0x33010, 1051 .mnd_width = 0, 1052 .hid_width = 5, 1053 .parent_map = gcc_parent_map_1, 1054 .freq_tbl = ftbl_pdm2_clk_src, 1055 .clkr.hw.init = &(struct clk_init_data){ 1056 .name = "pdm2_clk_src", 1057 .parent_data = gcc_parent_data_1, 1058 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1059 .ops = &clk_rcg2_ops, 1060 }, 1061}; 1062 1063static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { 1064 F(144000, P_XO, 16, 3, 25), 1065 F(400000, P_XO, 12, 1, 4), 1066 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1067 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1068 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1069 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1070 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1071 { } 1072}; 1073 1074static struct clk_rcg2 sdcc2_apps_clk_src = { 1075 .cmd_rcgr = 0x14010, 1076 .mnd_width = 8, 1077 .hid_width = 5, 1078 .parent_map = gcc_parent_map_4, 1079 .freq_tbl = ftbl_sdcc2_apps_clk_src, 1080 .clkr.hw.init = &(struct clk_init_data){ 1081 .name = "sdcc2_apps_clk_src", 1082 .parent_data = gcc_parent_data_4, 1083 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1084 .ops = &clk_rcg2_floor_ops, 1085 }, 1086}; 1087 1088static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = { 1089 F(144000, P_XO, 16, 3, 25), 1090 F(400000, P_XO, 12, 1, 4), 1091 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), 1092 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), 1093 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 1094 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1095 { } 1096}; 1097 1098static struct clk_rcg2 sdcc4_apps_clk_src = { 1099 .cmd_rcgr = 0x16010, 1100 .mnd_width = 8, 1101 .hid_width = 5, 1102 .parent_map = gcc_parent_map_1, 1103 .freq_tbl = ftbl_sdcc4_apps_clk_src, 1104 .clkr.hw.init = &(struct clk_init_data){ 1105 .name = "sdcc4_apps_clk_src", 1106 .parent_data = gcc_parent_data_1, 1107 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1108 .ops = &clk_rcg2_floor_ops, 1109 }, 1110}; 1111 1112static const struct freq_tbl ftbl_tsif_ref_clk_src[] = { 1113 F(105495, P_XO, 1, 1, 182), 1114 { } 1115}; 1116 1117static struct clk_rcg2 tsif_ref_clk_src = { 1118 .cmd_rcgr = 0x36010, 1119 .mnd_width = 8, 1120 .hid_width = 5, 1121 .parent_map = gcc_parent_map_5, 1122 .freq_tbl = ftbl_tsif_ref_clk_src, 1123 .clkr.hw.init = &(struct clk_init_data){ 1124 .name = "tsif_ref_clk_src", 1125 .parent_data = gcc_parent_data_5, 1126 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1127 .ops = &clk_rcg2_ops, 1128 }, 1129}; 1130 1131static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { 1132 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 1133 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 1134 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), 1135 { } 1136}; 1137 1138static struct clk_rcg2 ufs_axi_clk_src = { 1139 .cmd_rcgr = 0x75018, 1140 .mnd_width = 8, 1141 .hid_width = 5, 1142 .parent_map = gcc_parent_map_0, 1143 .freq_tbl = ftbl_ufs_axi_clk_src, 1144 .clkr.hw.init = &(struct clk_init_data){ 1145 .name = "ufs_axi_clk_src", 1146 .parent_data = gcc_parent_data_0, 1147 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1148 .ops = &clk_rcg2_ops, 1149 }, 1150}; 1151 1152static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { 1153 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 1154 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 1155 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1156 { } 1157}; 1158 1159static struct clk_rcg2 ufs_unipro_core_clk_src = { 1160 .cmd_rcgr = 0x76028, 1161 .mnd_width = 8, 1162 .hid_width = 5, 1163 .parent_map = gcc_parent_map_0, 1164 .freq_tbl = ftbl_ufs_unipro_core_clk_src, 1165 .clkr.hw.init = &(struct clk_init_data){ 1166 .name = "ufs_unipro_core_clk_src", 1167 .parent_data = gcc_parent_data_0, 1168 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1169 .ops = &clk_rcg2_ops, 1170 }, 1171}; 1172 1173static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 1174 F(19200000, P_XO, 1, 0, 0), 1175 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), 1176 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 1177 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1178 { } 1179}; 1180 1181static struct clk_rcg2 usb30_master_clk_src = { 1182 .cmd_rcgr = 0xf014, 1183 .mnd_width = 8, 1184 .hid_width = 5, 1185 .parent_map = gcc_parent_map_0, 1186 .freq_tbl = ftbl_usb30_master_clk_src, 1187 .clkr.hw.init = &(struct clk_init_data){ 1188 .name = "usb30_master_clk_src", 1189 .parent_data = gcc_parent_data_0, 1190 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1191 .ops = &clk_rcg2_ops, 1192 }, 1193}; 1194 1195static struct clk_rcg2 usb30_mock_utmi_clk_src = { 1196 .cmd_rcgr = 0xf028, 1197 .mnd_width = 0, 1198 .hid_width = 5, 1199 .parent_map = gcc_parent_map_0, 1200 .freq_tbl = ftbl_hmss_rbcpr_clk_src, 1201 .clkr.hw.init = &(struct clk_init_data){ 1202 .name = "usb30_mock_utmi_clk_src", 1203 .parent_data = gcc_parent_data_0, 1204 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1205 .ops = &clk_rcg2_ops, 1206 }, 1207}; 1208 1209static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { 1210 F(1200000, P_XO, 16, 0, 0), 1211 { } 1212}; 1213 1214static struct clk_rcg2 usb3_phy_aux_clk_src = { 1215 .cmd_rcgr = 0x5000c, 1216 .mnd_width = 0, 1217 .hid_width = 5, 1218 .parent_map = gcc_parent_map_3, 1219 .freq_tbl = ftbl_usb3_phy_aux_clk_src, 1220 .clkr.hw.init = &(struct clk_init_data){ 1221 .name = "usb3_phy_aux_clk_src", 1222 .parent_data = gcc_parent_data_3, 1223 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1224 .ops = &clk_rcg2_ops, 1225 }, 1226}; 1227 1228static struct clk_branch gcc_aggre1_noc_xo_clk = { 1229 .halt_reg = 0x8202c, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x8202c, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "gcc_aggre1_noc_xo_clk", 1236 .ops = &clk_branch2_ops, 1237 }, 1238 }, 1239}; 1240 1241static struct clk_branch gcc_aggre1_ufs_axi_clk = { 1242 .halt_reg = 0x82028, 1243 .halt_check = BRANCH_HALT, 1244 .clkr = { 1245 .enable_reg = 0x82028, 1246 .enable_mask = BIT(0), 1247 .hw.init = &(struct clk_init_data){ 1248 .name = "gcc_aggre1_ufs_axi_clk", 1249 .parent_hws = (const struct clk_hw *[]) { 1250 &ufs_axi_clk_src.clkr.hw, 1251 }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 .ops = &clk_branch2_ops, 1255 }, 1256 }, 1257}; 1258 1259static struct clk_branch gcc_aggre1_usb3_axi_clk = { 1260 .halt_reg = 0x82024, 1261 .halt_check = BRANCH_HALT, 1262 .clkr = { 1263 .enable_reg = 0x82024, 1264 .enable_mask = BIT(0), 1265 .hw.init = &(struct clk_init_data){ 1266 .name = "gcc_aggre1_usb3_axi_clk", 1267 .parent_hws = (const struct clk_hw *[]) { 1268 &usb30_master_clk_src.clkr.hw, 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275}; 1276 1277static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = { 1278 .halt_reg = 0x48090, 1279 .halt_check = BRANCH_HALT, 1280 .clkr = { 1281 .enable_reg = 0x48090, 1282 .enable_mask = BIT(0), 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "gcc_apss_qdss_tsctr_div2_clk", 1285 .ops = &clk_branch2_ops, 1286 }, 1287 }, 1288}; 1289 1290static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = { 1291 .halt_reg = 0x48094, 1292 .halt_check = BRANCH_HALT, 1293 .clkr = { 1294 .enable_reg = 0x48094, 1295 .enable_mask = BIT(0), 1296 .hw.init = &(struct clk_init_data){ 1297 .name = "gcc_apss_qdss_tsctr_div8_clk", 1298 .ops = &clk_branch2_ops, 1299 }, 1300 }, 1301}; 1302 1303static struct clk_branch gcc_bimc_hmss_axi_clk = { 1304 .halt_reg = 0x48004, 1305 .halt_check = BRANCH_HALT_VOTED, 1306 .clkr = { 1307 .enable_reg = 0x52004, 1308 .enable_mask = BIT(22), 1309 .hw.init = &(struct clk_init_data){ 1310 .name = "gcc_bimc_hmss_axi_clk", 1311 .ops = &clk_branch2_ops, 1312 }, 1313 }, 1314}; 1315 1316static struct clk_branch gcc_bimc_mss_q6_axi_clk = { 1317 .halt_reg = 0x4401c, 1318 .halt_check = BRANCH_HALT, 1319 .clkr = { 1320 .enable_reg = 0x4401c, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(struct clk_init_data){ 1323 .name = "gcc_bimc_mss_q6_axi_clk", 1324 .ops = &clk_branch2_ops, 1325 }, 1326 }, 1327}; 1328 1329static struct clk_branch gcc_mss_cfg_ahb_clk = { 1330 .halt_reg = 0x8a000, 1331 .halt_check = BRANCH_HALT, 1332 .clkr = { 1333 .enable_reg = 0x8a000, 1334 .enable_mask = BIT(0), 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "gcc_mss_cfg_ahb_clk", 1337 .ops = &clk_branch2_ops, 1338 }, 1339 }, 1340}; 1341 1342static struct clk_branch gcc_mss_snoc_axi_clk = { 1343 .halt_reg = 0x8a03c, 1344 .halt_check = BRANCH_HALT, 1345 .clkr = { 1346 .enable_reg = 0x8a03c, 1347 .enable_mask = BIT(0), 1348 .hw.init = &(struct clk_init_data){ 1349 .name = "gcc_mss_snoc_axi_clk", 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353}; 1354 1355static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { 1356 .halt_reg = 0x8a004, 1357 .halt_check = BRANCH_HALT, 1358 .clkr = { 1359 .enable_reg = 0x8a004, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(struct clk_init_data){ 1362 .name = "gcc_mss_mnoc_bimc_axi_clk", 1363 .ops = &clk_branch2_ops, 1364 }, 1365 }, 1366}; 1367 1368static struct clk_branch gcc_boot_rom_ahb_clk = { 1369 .halt_reg = 0x38004, 1370 .halt_check = BRANCH_HALT_VOTED, 1371 .hwcg_reg = 0x38004, 1372 .hwcg_bit = 1, 1373 .clkr = { 1374 .enable_reg = 0x52004, 1375 .enable_mask = BIT(10), 1376 .hw.init = &(struct clk_init_data){ 1377 .name = "gcc_boot_rom_ahb_clk", 1378 .ops = &clk_branch2_ops, 1379 }, 1380 }, 1381}; 1382 1383static struct clk_branch gcc_mmss_gpll0_clk = { 1384 .halt_check = BRANCH_HALT_DELAY, 1385 .clkr = { 1386 .enable_reg = 0x5200c, 1387 .enable_mask = BIT(1), 1388 .hw.init = &(struct clk_init_data){ 1389 .name = "gcc_mmss_gpll0_clk", 1390 .parent_hws = (const struct clk_hw *[]) { 1391 &gpll0_out_main.clkr.hw, 1392 }, 1393 .num_parents = 1, 1394 .ops = &clk_branch2_ops, 1395 }, 1396 }, 1397}; 1398 1399static struct clk_branch gcc_mss_gpll0_div_clk_src = { 1400 .halt_check = BRANCH_HALT_DELAY, 1401 .clkr = { 1402 .enable_reg = 0x5200c, 1403 .enable_mask = BIT(2), 1404 .hw.init = &(struct clk_init_data){ 1405 .name = "gcc_mss_gpll0_div_clk_src", 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409}; 1410 1411static struct clk_branch gcc_blsp1_ahb_clk = { 1412 .halt_reg = 0x17004, 1413 .halt_check = BRANCH_HALT_VOTED, 1414 .clkr = { 1415 .enable_reg = 0x52004, 1416 .enable_mask = BIT(17), 1417 .hw.init = &(struct clk_init_data){ 1418 .name = "gcc_blsp1_ahb_clk", 1419 .ops = &clk_branch2_ops, 1420 }, 1421 }, 1422}; 1423 1424static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1425 .halt_reg = 0x19008, 1426 .halt_check = BRANCH_HALT, 1427 .clkr = { 1428 .enable_reg = 0x19008, 1429 .enable_mask = BIT(0), 1430 .hw.init = &(struct clk_init_data){ 1431 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1432 .parent_hws = (const struct clk_hw *[]) { 1433 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1434 }, 1435 .num_parents = 1, 1436 .flags = CLK_SET_RATE_PARENT, 1437 .ops = &clk_branch2_ops, 1438 }, 1439 }, 1440}; 1441 1442static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1443 .halt_reg = 0x19004, 1444 .halt_check = BRANCH_HALT, 1445 .clkr = { 1446 .enable_reg = 0x19004, 1447 .enable_mask = BIT(0), 1448 .hw.init = &(struct clk_init_data){ 1449 .name = "gcc_blsp1_qup1_spi_apps_clk", 1450 .parent_hws = (const struct clk_hw *[]) { 1451 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1452 }, 1453 .num_parents = 1, 1454 .flags = CLK_SET_RATE_PARENT, 1455 .ops = &clk_branch2_ops, 1456 }, 1457 }, 1458}; 1459 1460static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1461 .halt_reg = 0x1b008, 1462 .halt_check = BRANCH_HALT, 1463 .clkr = { 1464 .enable_reg = 0x1b008, 1465 .enable_mask = BIT(0), 1466 .hw.init = &(struct clk_init_data){ 1467 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1468 .parent_hws = (const struct clk_hw *[]) { 1469 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1470 }, 1471 .num_parents = 1, 1472 .flags = CLK_SET_RATE_PARENT, 1473 .ops = &clk_branch2_ops, 1474 }, 1475 }, 1476}; 1477 1478static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1479 .halt_reg = 0x1b004, 1480 .halt_check = BRANCH_HALT, 1481 .clkr = { 1482 .enable_reg = 0x1b004, 1483 .enable_mask = BIT(0), 1484 .hw.init = &(struct clk_init_data){ 1485 .name = "gcc_blsp1_qup2_spi_apps_clk", 1486 .parent_hws = (const struct clk_hw *[]) { 1487 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1488 }, 1489 .num_parents = 1, 1490 .flags = CLK_SET_RATE_PARENT, 1491 .ops = &clk_branch2_ops, 1492 }, 1493 }, 1494}; 1495 1496static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1497 .halt_reg = 0x1d008, 1498 .halt_check = BRANCH_HALT, 1499 .clkr = { 1500 .enable_reg = 0x1d008, 1501 .enable_mask = BIT(0), 1502 .hw.init = &(struct clk_init_data){ 1503 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1504 .parent_hws = (const struct clk_hw *[]) { 1505 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1506 }, 1507 .num_parents = 1, 1508 .flags = CLK_SET_RATE_PARENT, 1509 .ops = &clk_branch2_ops, 1510 }, 1511 }, 1512}; 1513 1514static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1515 .halt_reg = 0x1d004, 1516 .halt_check = BRANCH_HALT, 1517 .clkr = { 1518 .enable_reg = 0x1d004, 1519 .enable_mask = BIT(0), 1520 .hw.init = &(struct clk_init_data){ 1521 .name = "gcc_blsp1_qup3_spi_apps_clk", 1522 .parent_hws = (const struct clk_hw *[]) { 1523 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1524 }, 1525 .num_parents = 1, 1526 .flags = CLK_SET_RATE_PARENT, 1527 .ops = &clk_branch2_ops, 1528 }, 1529 }, 1530}; 1531 1532static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1533 .halt_reg = 0x1f008, 1534 .halt_check = BRANCH_HALT, 1535 .clkr = { 1536 .enable_reg = 0x1f008, 1537 .enable_mask = BIT(0), 1538 .hw.init = &(struct clk_init_data){ 1539 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1540 .parent_hws = (const struct clk_hw *[]) { 1541 &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1542 }, 1543 .num_parents = 1, 1544 .flags = CLK_SET_RATE_PARENT, 1545 .ops = &clk_branch2_ops, 1546 }, 1547 }, 1548}; 1549 1550static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1551 .halt_reg = 0x1f004, 1552 .halt_check = BRANCH_HALT, 1553 .clkr = { 1554 .enable_reg = 0x1f004, 1555 .enable_mask = BIT(0), 1556 .hw.init = &(struct clk_init_data){ 1557 .name = "gcc_blsp1_qup4_spi_apps_clk", 1558 .parent_hws = (const struct clk_hw *[]) { 1559 &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1560 }, 1561 .num_parents = 1, 1562 .flags = CLK_SET_RATE_PARENT, 1563 .ops = &clk_branch2_ops, 1564 }, 1565 }, 1566}; 1567 1568static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1569 .halt_reg = 0x21008, 1570 .halt_check = BRANCH_HALT, 1571 .clkr = { 1572 .enable_reg = 0x21008, 1573 .enable_mask = BIT(0), 1574 .hw.init = &(struct clk_init_data){ 1575 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1576 .parent_hws = (const struct clk_hw *[]) { 1577 &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1578 }, 1579 .num_parents = 1, 1580 .flags = CLK_SET_RATE_PARENT, 1581 .ops = &clk_branch2_ops, 1582 }, 1583 }, 1584}; 1585 1586static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1587 .halt_reg = 0x21004, 1588 .halt_check = BRANCH_HALT, 1589 .clkr = { 1590 .enable_reg = 0x21004, 1591 .enable_mask = BIT(0), 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "gcc_blsp1_qup5_spi_apps_clk", 1594 .parent_hws = (const struct clk_hw *[]) { 1595 &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1596 }, 1597 .num_parents = 1, 1598 .flags = CLK_SET_RATE_PARENT, 1599 .ops = &clk_branch2_ops, 1600 }, 1601 }, 1602}; 1603 1604static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1605 .halt_reg = 0x23008, 1606 .halt_check = BRANCH_HALT, 1607 .clkr = { 1608 .enable_reg = 0x23008, 1609 .enable_mask = BIT(0), 1610 .hw.init = &(struct clk_init_data){ 1611 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1612 .parent_hws = (const struct clk_hw *[]) { 1613 &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1614 }, 1615 .num_parents = 1, 1616 .flags = CLK_SET_RATE_PARENT, 1617 .ops = &clk_branch2_ops, 1618 }, 1619 }, 1620}; 1621 1622static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1623 .halt_reg = 0x23004, 1624 .halt_check = BRANCH_HALT, 1625 .clkr = { 1626 .enable_reg = 0x23004, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "gcc_blsp1_qup6_spi_apps_clk", 1630 .parent_hws = (const struct clk_hw *[]) { 1631 &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638}; 1639 1640static struct clk_branch gcc_blsp1_sleep_clk = { 1641 .halt_reg = 0x17008, 1642 .halt_check = BRANCH_HALT_VOTED, 1643 .clkr = { 1644 .enable_reg = 0x52004, 1645 .enable_mask = BIT(16), 1646 .hw.init = &(struct clk_init_data){ 1647 .name = "gcc_blsp1_sleep_clk", 1648 .ops = &clk_branch2_ops, 1649 }, 1650 }, 1651}; 1652 1653static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1654 .halt_reg = 0x1a004, 1655 .halt_check = BRANCH_HALT, 1656 .clkr = { 1657 .enable_reg = 0x1a004, 1658 .enable_mask = BIT(0), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "gcc_blsp1_uart1_apps_clk", 1661 .parent_hws = (const struct clk_hw *[]) { 1662 &blsp1_uart1_apps_clk_src.clkr.hw, 1663 }, 1664 .num_parents = 1, 1665 .flags = CLK_SET_RATE_PARENT, 1666 .ops = &clk_branch2_ops, 1667 }, 1668 }, 1669}; 1670 1671static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1672 .halt_reg = 0x1c004, 1673 .halt_check = BRANCH_HALT, 1674 .clkr = { 1675 .enable_reg = 0x1c004, 1676 .enable_mask = BIT(0), 1677 .hw.init = &(struct clk_init_data){ 1678 .name = "gcc_blsp1_uart2_apps_clk", 1679 .parent_hws = (const struct clk_hw *[]) { 1680 &blsp1_uart2_apps_clk_src.clkr.hw, 1681 }, 1682 .num_parents = 1, 1683 .flags = CLK_SET_RATE_PARENT, 1684 .ops = &clk_branch2_ops, 1685 }, 1686 }, 1687}; 1688 1689static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1690 .halt_reg = 0x1e004, 1691 .halt_check = BRANCH_HALT, 1692 .clkr = { 1693 .enable_reg = 0x1e004, 1694 .enable_mask = BIT(0), 1695 .hw.init = &(struct clk_init_data){ 1696 .name = "gcc_blsp1_uart3_apps_clk", 1697 .parent_hws = (const struct clk_hw *[]) { 1698 &blsp1_uart3_apps_clk_src.clkr.hw, 1699 }, 1700 .num_parents = 1, 1701 .flags = CLK_SET_RATE_PARENT, 1702 .ops = &clk_branch2_ops, 1703 }, 1704 }, 1705}; 1706 1707static struct clk_branch gcc_blsp2_ahb_clk = { 1708 .halt_reg = 0x25004, 1709 .halt_check = BRANCH_HALT_VOTED, 1710 .clkr = { 1711 .enable_reg = 0x52004, 1712 .enable_mask = BIT(15), 1713 .hw.init = &(struct clk_init_data){ 1714 .name = "gcc_blsp2_ahb_clk", 1715 .ops = &clk_branch2_ops, 1716 }, 1717 }, 1718}; 1719 1720static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1721 .halt_reg = 0x26008, 1722 .halt_check = BRANCH_HALT, 1723 .clkr = { 1724 .enable_reg = 0x26008, 1725 .enable_mask = BIT(0), 1726 .hw.init = &(struct clk_init_data){ 1727 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1728 .parent_hws = (const struct clk_hw *[]) { 1729 &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1730 }, 1731 .num_parents = 1, 1732 .flags = CLK_SET_RATE_PARENT, 1733 .ops = &clk_branch2_ops, 1734 }, 1735 }, 1736}; 1737 1738static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1739 .halt_reg = 0x26004, 1740 .halt_check = BRANCH_HALT, 1741 .clkr = { 1742 .enable_reg = 0x26004, 1743 .enable_mask = BIT(0), 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "gcc_blsp2_qup1_spi_apps_clk", 1746 .parent_hws = (const struct clk_hw *[]) { 1747 &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1748 }, 1749 .num_parents = 1, 1750 .flags = CLK_SET_RATE_PARENT, 1751 .ops = &clk_branch2_ops, 1752 }, 1753 }, 1754}; 1755 1756static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1757 .halt_reg = 0x28008, 1758 .halt_check = BRANCH_HALT, 1759 .clkr = { 1760 .enable_reg = 0x28008, 1761 .enable_mask = BIT(0), 1762 .hw.init = &(struct clk_init_data){ 1763 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1764 .parent_hws = (const struct clk_hw *[]) { 1765 &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1766 }, 1767 .num_parents = 1, 1768 .flags = CLK_SET_RATE_PARENT, 1769 .ops = &clk_branch2_ops, 1770 }, 1771 }, 1772}; 1773 1774static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1775 .halt_reg = 0x28004, 1776 .halt_check = BRANCH_HALT, 1777 .clkr = { 1778 .enable_reg = 0x28004, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "gcc_blsp2_qup2_spi_apps_clk", 1782 .parent_hws = (const struct clk_hw *[]) { 1783 &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1784 }, 1785 .num_parents = 1, 1786 .flags = CLK_SET_RATE_PARENT, 1787 .ops = &clk_branch2_ops, 1788 }, 1789 }, 1790}; 1791 1792static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1793 .halt_reg = 0x2a008, 1794 .halt_check = BRANCH_HALT, 1795 .clkr = { 1796 .enable_reg = 0x2a008, 1797 .enable_mask = BIT(0), 1798 .hw.init = &(struct clk_init_data){ 1799 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1800 .parent_hws = (const struct clk_hw *[]) { 1801 &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1802 }, 1803 .num_parents = 1, 1804 .flags = CLK_SET_RATE_PARENT, 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808}; 1809 1810static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1811 .halt_reg = 0x2a004, 1812 .halt_check = BRANCH_HALT, 1813 .clkr = { 1814 .enable_reg = 0x2a004, 1815 .enable_mask = BIT(0), 1816 .hw.init = &(struct clk_init_data){ 1817 .name = "gcc_blsp2_qup3_spi_apps_clk", 1818 .parent_hws = (const struct clk_hw *[]) { 1819 &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1820 }, 1821 .num_parents = 1, 1822 .flags = CLK_SET_RATE_PARENT, 1823 .ops = &clk_branch2_ops, 1824 }, 1825 }, 1826}; 1827 1828static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1829 .halt_reg = 0x2c008, 1830 .halt_check = BRANCH_HALT, 1831 .clkr = { 1832 .enable_reg = 0x2c008, 1833 .enable_mask = BIT(0), 1834 .hw.init = &(struct clk_init_data){ 1835 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1836 .parent_hws = (const struct clk_hw *[]) { 1837 &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1838 }, 1839 .num_parents = 1, 1840 .flags = CLK_SET_RATE_PARENT, 1841 .ops = &clk_branch2_ops, 1842 }, 1843 }, 1844}; 1845 1846static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1847 .halt_reg = 0x2c004, 1848 .halt_check = BRANCH_HALT, 1849 .clkr = { 1850 .enable_reg = 0x2c004, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(struct clk_init_data){ 1853 .name = "gcc_blsp2_qup4_spi_apps_clk", 1854 .parent_hws = (const struct clk_hw *[]) { 1855 &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1856 }, 1857 .num_parents = 1, 1858 .flags = CLK_SET_RATE_PARENT, 1859 .ops = &clk_branch2_ops, 1860 }, 1861 }, 1862}; 1863 1864static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1865 .halt_reg = 0x2e008, 1866 .halt_check = BRANCH_HALT, 1867 .clkr = { 1868 .enable_reg = 0x2e008, 1869 .enable_mask = BIT(0), 1870 .hw.init = &(struct clk_init_data){ 1871 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1872 .parent_hws = (const struct clk_hw *[]) { 1873 &blsp2_qup5_i2c_apps_clk_src.clkr.hw, 1874 }, 1875 .num_parents = 1, 1876 .flags = CLK_SET_RATE_PARENT, 1877 .ops = &clk_branch2_ops, 1878 }, 1879 }, 1880}; 1881 1882static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1883 .halt_reg = 0x2e004, 1884 .halt_check = BRANCH_HALT, 1885 .clkr = { 1886 .enable_reg = 0x2e004, 1887 .enable_mask = BIT(0), 1888 .hw.init = &(struct clk_init_data){ 1889 .name = "gcc_blsp2_qup5_spi_apps_clk", 1890 .parent_hws = (const struct clk_hw *[]) { 1891 &blsp2_qup5_spi_apps_clk_src.clkr.hw, 1892 }, 1893 .num_parents = 1, 1894 .flags = CLK_SET_RATE_PARENT, 1895 .ops = &clk_branch2_ops, 1896 }, 1897 }, 1898}; 1899 1900static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1901 .halt_reg = 0x30008, 1902 .halt_check = BRANCH_HALT, 1903 .clkr = { 1904 .enable_reg = 0x30008, 1905 .enable_mask = BIT(0), 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1908 .parent_hws = (const struct clk_hw *[]) { 1909 &blsp2_qup6_i2c_apps_clk_src.clkr.hw, 1910 }, 1911 .num_parents = 1, 1912 .flags = CLK_SET_RATE_PARENT, 1913 .ops = &clk_branch2_ops, 1914 }, 1915 }, 1916}; 1917 1918static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1919 .halt_reg = 0x30004, 1920 .halt_check = BRANCH_HALT, 1921 .clkr = { 1922 .enable_reg = 0x30004, 1923 .enable_mask = BIT(0), 1924 .hw.init = &(struct clk_init_data){ 1925 .name = "gcc_blsp2_qup6_spi_apps_clk", 1926 .parent_hws = (const struct clk_hw *[]) { 1927 &blsp2_qup6_spi_apps_clk_src.clkr.hw, 1928 }, 1929 .num_parents = 1, 1930 .flags = CLK_SET_RATE_PARENT, 1931 .ops = &clk_branch2_ops, 1932 }, 1933 }, 1934}; 1935 1936static struct clk_branch gcc_blsp2_sleep_clk = { 1937 .halt_reg = 0x25008, 1938 .halt_check = BRANCH_HALT_VOTED, 1939 .clkr = { 1940 .enable_reg = 0x52004, 1941 .enable_mask = BIT(14), 1942 .hw.init = &(struct clk_init_data){ 1943 .name = "gcc_blsp2_sleep_clk", 1944 .ops = &clk_branch2_ops, 1945 }, 1946 }, 1947}; 1948 1949static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1950 .halt_reg = 0x27004, 1951 .halt_check = BRANCH_HALT, 1952 .clkr = { 1953 .enable_reg = 0x27004, 1954 .enable_mask = BIT(0), 1955 .hw.init = &(struct clk_init_data){ 1956 .name = "gcc_blsp2_uart1_apps_clk", 1957 .parent_hws = (const struct clk_hw *[]) { 1958 &blsp2_uart1_apps_clk_src.clkr.hw, 1959 }, 1960 .num_parents = 1, 1961 .flags = CLK_SET_RATE_PARENT, 1962 .ops = &clk_branch2_ops, 1963 }, 1964 }, 1965}; 1966 1967static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1968 .halt_reg = 0x29004, 1969 .halt_check = BRANCH_HALT, 1970 .clkr = { 1971 .enable_reg = 0x29004, 1972 .enable_mask = BIT(0), 1973 .hw.init = &(struct clk_init_data){ 1974 .name = "gcc_blsp2_uart2_apps_clk", 1975 .parent_hws = (const struct clk_hw *[]) { 1976 &blsp2_uart2_apps_clk_src.clkr.hw, 1977 }, 1978 .num_parents = 1, 1979 .flags = CLK_SET_RATE_PARENT, 1980 .ops = &clk_branch2_ops, 1981 }, 1982 }, 1983}; 1984 1985static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1986 .halt_reg = 0x2b004, 1987 .halt_check = BRANCH_HALT, 1988 .clkr = { 1989 .enable_reg = 0x2b004, 1990 .enable_mask = BIT(0), 1991 .hw.init = &(struct clk_init_data){ 1992 .name = "gcc_blsp2_uart3_apps_clk", 1993 .parent_hws = (const struct clk_hw *[]) { 1994 &blsp2_uart3_apps_clk_src.clkr.hw, 1995 }, 1996 .num_parents = 1, 1997 .flags = CLK_SET_RATE_PARENT, 1998 .ops = &clk_branch2_ops, 1999 }, 2000 }, 2001}; 2002 2003static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { 2004 .halt_reg = 0x5018, 2005 .halt_check = BRANCH_HALT, 2006 .clkr = { 2007 .enable_reg = 0x5018, 2008 .enable_mask = BIT(0), 2009 .hw.init = &(struct clk_init_data){ 2010 .name = "gcc_cfg_noc_usb3_axi_clk", 2011 .parent_hws = (const struct clk_hw *[]) { 2012 &usb30_master_clk_src.clkr.hw, 2013 }, 2014 .num_parents = 1, 2015 .flags = CLK_SET_RATE_PARENT, 2016 .ops = &clk_branch2_ops, 2017 }, 2018 }, 2019}; 2020 2021static struct clk_branch gcc_gp1_clk = { 2022 .halt_reg = 0x64000, 2023 .halt_check = BRANCH_HALT, 2024 .clkr = { 2025 .enable_reg = 0x64000, 2026 .enable_mask = BIT(0), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "gcc_gp1_clk", 2029 .parent_hws = (const struct clk_hw *[]) { 2030 &gp1_clk_src.clkr.hw, 2031 }, 2032 .num_parents = 1, 2033 .flags = CLK_SET_RATE_PARENT, 2034 .ops = &clk_branch2_ops, 2035 }, 2036 }, 2037}; 2038 2039static struct clk_branch gcc_gp2_clk = { 2040 .halt_reg = 0x65000, 2041 .halt_check = BRANCH_HALT, 2042 .clkr = { 2043 .enable_reg = 0x65000, 2044 .enable_mask = BIT(0), 2045 .hw.init = &(struct clk_init_data){ 2046 .name = "gcc_gp2_clk", 2047 .parent_hws = (const struct clk_hw *[]) { 2048 &gp2_clk_src.clkr.hw, 2049 }, 2050 .num_parents = 1, 2051 .flags = CLK_SET_RATE_PARENT, 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055}; 2056 2057static struct clk_branch gcc_gp3_clk = { 2058 .halt_reg = 0x66000, 2059 .halt_check = BRANCH_HALT, 2060 .clkr = { 2061 .enable_reg = 0x66000, 2062 .enable_mask = BIT(0), 2063 .hw.init = &(struct clk_init_data){ 2064 .name = "gcc_gp3_clk", 2065 .parent_hws = (const struct clk_hw *[]) { 2066 &gp3_clk_src.clkr.hw, 2067 }, 2068 .num_parents = 1, 2069 .flags = CLK_SET_RATE_PARENT, 2070 .ops = &clk_branch2_ops, 2071 }, 2072 }, 2073}; 2074 2075static struct clk_branch gcc_bimc_gfx_clk = { 2076 .halt_reg = 0x46040, 2077 .halt_check = BRANCH_HALT, 2078 .clkr = { 2079 .enable_reg = 0x46040, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "gcc_bimc_gfx_clk", 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086}; 2087 2088static struct clk_branch gcc_gpu_bimc_gfx_clk = { 2089 .halt_reg = 0x71010, 2090 .halt_check = BRANCH_HALT, 2091 .clkr = { 2092 .enable_reg = 0x71010, 2093 .enable_mask = BIT(0), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "gcc_gpu_bimc_gfx_clk", 2096 .ops = &clk_branch2_ops, 2097 }, 2098 }, 2099}; 2100 2101static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { 2102 .halt_reg = 0x7100c, 2103 .halt_check = BRANCH_HALT, 2104 .clkr = { 2105 .enable_reg = 0x7100c, 2106 .enable_mask = BIT(0), 2107 .hw.init = &(struct clk_init_data){ 2108 .name = "gcc_gpu_bimc_gfx_src_clk", 2109 .ops = &clk_branch2_ops, 2110 }, 2111 }, 2112}; 2113 2114static struct clk_branch gcc_gpu_cfg_ahb_clk = { 2115 .halt_reg = 0x71004, 2116 .halt_check = BRANCH_HALT, 2117 .clkr = { 2118 .enable_reg = 0x71004, 2119 .enable_mask = BIT(0), 2120 .hw.init = &(struct clk_init_data){ 2121 .name = "gcc_gpu_cfg_ahb_clk", 2122 .ops = &clk_branch2_ops, 2123 /* 2124 * The GPU IOMMU depends on this clock and hypervisor 2125 * will crash the SoC if this clock goes down, due to 2126 * secure contexts protection. 2127 */ 2128 .flags = CLK_IS_CRITICAL, 2129 }, 2130 }, 2131}; 2132 2133static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { 2134 .halt_reg = 0x71018, 2135 .halt_check = BRANCH_HALT, 2136 .clkr = { 2137 .enable_reg = 0x71018, 2138 .enable_mask = BIT(0), 2139 .hw.init = &(struct clk_init_data){ 2140 .name = "gcc_gpu_snoc_dvm_gfx_clk", 2141 .ops = &clk_branch2_ops, 2142 }, 2143 }, 2144}; 2145 2146static struct clk_branch gcc_hmss_ahb_clk = { 2147 .halt_reg = 0x48000, 2148 .halt_check = BRANCH_HALT_VOTED, 2149 .clkr = { 2150 .enable_reg = 0x52004, 2151 .enable_mask = BIT(21), 2152 .hw.init = &(struct clk_init_data){ 2153 .name = "gcc_hmss_ahb_clk", 2154 .parent_hws = (const struct clk_hw *[]) { 2155 &hmss_ahb_clk_src.clkr.hw, 2156 }, 2157 .num_parents = 1, 2158 .flags = CLK_SET_RATE_PARENT, 2159 .ops = &clk_branch2_ops, 2160 }, 2161 }, 2162}; 2163 2164static struct clk_branch gcc_hmss_at_clk = { 2165 .halt_reg = 0x48010, 2166 .halt_check = BRANCH_HALT, 2167 .clkr = { 2168 .enable_reg = 0x48010, 2169 .enable_mask = BIT(0), 2170 .hw.init = &(struct clk_init_data){ 2171 .name = "gcc_hmss_at_clk", 2172 .ops = &clk_branch2_ops, 2173 }, 2174 }, 2175}; 2176 2177static struct clk_branch gcc_hmss_rbcpr_clk = { 2178 .halt_reg = 0x48008, 2179 .halt_check = BRANCH_HALT, 2180 .clkr = { 2181 .enable_reg = 0x48008, 2182 .enable_mask = BIT(0), 2183 .hw.init = &(struct clk_init_data){ 2184 .name = "gcc_hmss_rbcpr_clk", 2185 .parent_hws = (const struct clk_hw *[]) { 2186 &hmss_rbcpr_clk_src.clkr.hw, 2187 }, 2188 .num_parents = 1, 2189 .flags = CLK_SET_RATE_PARENT, 2190 .ops = &clk_branch2_ops, 2191 }, 2192 }, 2193}; 2194 2195static struct clk_branch gcc_hmss_trig_clk = { 2196 .halt_reg = 0x4800c, 2197 .halt_check = BRANCH_HALT, 2198 .clkr = { 2199 .enable_reg = 0x4800c, 2200 .enable_mask = BIT(0), 2201 .hw.init = &(struct clk_init_data){ 2202 .name = "gcc_hmss_trig_clk", 2203 .ops = &clk_branch2_ops, 2204 }, 2205 }, 2206}; 2207 2208static struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { 2209 F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 2210 F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), 2211 { } 2212}; 2213 2214static struct clk_rcg2 hmss_gpll0_clk_src = { 2215 .cmd_rcgr = 0x4805c, 2216 .hid_width = 5, 2217 .parent_map = gcc_parent_map_1, 2218 .freq_tbl = ftbl_hmss_gpll0_clk_src, 2219 .clkr.hw.init = &(struct clk_init_data) { 2220 .name = "hmss_gpll0_clk_src", 2221 .parent_data = gcc_parent_data_1, 2222 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 2223 .ops = &clk_rcg2_ops, 2224 }, 2225}; 2226 2227static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 2228 .halt_reg = 0x9004, 2229 .halt_check = BRANCH_HALT, 2230 .clkr = { 2231 .enable_reg = 0x9004, 2232 .enable_mask = BIT(0), 2233 .hw.init = &(struct clk_init_data){ 2234 .name = "gcc_mmss_noc_cfg_ahb_clk", 2235 .ops = &clk_branch2_ops, 2236 /* 2237 * Any access to mmss depends on this clock. 2238 * Gating this clock has been shown to crash the system 2239 * when mmssnoc_axi_rpm_clk is inited in rpmcc. 2240 */ 2241 .flags = CLK_IS_CRITICAL, 2242 }, 2243 }, 2244}; 2245 2246static struct clk_branch gcc_mmss_qm_ahb_clk = { 2247 .halt_reg = 0x9030, 2248 .halt_check = BRANCH_HALT, 2249 .clkr = { 2250 .enable_reg = 0x9030, 2251 .enable_mask = BIT(0), 2252 .hw.init = &(struct clk_init_data){ 2253 .name = "gcc_mmss_qm_ahb_clk", 2254 .ops = &clk_branch2_ops, 2255 }, 2256 }, 2257}; 2258 2259static struct clk_branch gcc_mmss_qm_core_clk = { 2260 .halt_reg = 0x900c, 2261 .halt_check = BRANCH_HALT, 2262 .clkr = { 2263 .enable_reg = 0x900c, 2264 .enable_mask = BIT(0), 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "gcc_mmss_qm_core_clk", 2267 .ops = &clk_branch2_ops, 2268 }, 2269 }, 2270}; 2271 2272static struct clk_branch gcc_mmss_sys_noc_axi_clk = { 2273 .halt_reg = 0x9000, 2274 .halt_check = BRANCH_HALT, 2275 .clkr = { 2276 .enable_reg = 0x9000, 2277 .enable_mask = BIT(0), 2278 .hw.init = &(struct clk_init_data){ 2279 .name = "gcc_mmss_sys_noc_axi_clk", 2280 .ops = &clk_branch2_ops, 2281 }, 2282 }, 2283}; 2284 2285static struct clk_branch gcc_mss_at_clk = { 2286 .halt_reg = 0x8a00c, 2287 .halt_check = BRANCH_HALT, 2288 .clkr = { 2289 .enable_reg = 0x8a00c, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_mss_at_clk", 2293 .ops = &clk_branch2_ops, 2294 }, 2295 }, 2296}; 2297 2298static struct clk_branch gcc_pcie_0_aux_clk = { 2299 .halt_reg = 0x6b014, 2300 .halt_check = BRANCH_HALT, 2301 .clkr = { 2302 .enable_reg = 0x6b014, 2303 .enable_mask = BIT(0), 2304 .hw.init = &(struct clk_init_data){ 2305 .name = "gcc_pcie_0_aux_clk", 2306 .parent_hws = (const struct clk_hw *[]) { 2307 &pcie_aux_clk_src.clkr.hw, 2308 }, 2309 .num_parents = 1, 2310 .flags = CLK_SET_RATE_PARENT, 2311 .ops = &clk_branch2_ops, 2312 }, 2313 }, 2314}; 2315 2316static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 2317 .halt_reg = 0x6b010, 2318 .halt_check = BRANCH_HALT, 2319 .clkr = { 2320 .enable_reg = 0x6b010, 2321 .enable_mask = BIT(0), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "gcc_pcie_0_cfg_ahb_clk", 2324 .ops = &clk_branch2_ops, 2325 }, 2326 }, 2327}; 2328 2329static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 2330 .halt_reg = 0x6b00c, 2331 .halt_check = BRANCH_HALT, 2332 .clkr = { 2333 .enable_reg = 0x6b00c, 2334 .enable_mask = BIT(0), 2335 .hw.init = &(struct clk_init_data){ 2336 .name = "gcc_pcie_0_mstr_axi_clk", 2337 .ops = &clk_branch2_ops, 2338 }, 2339 }, 2340}; 2341 2342static struct clk_branch gcc_pcie_0_pipe_clk = { 2343 .halt_reg = 0x6b018, 2344 .halt_check = BRANCH_HALT_SKIP, 2345 .clkr = { 2346 .enable_reg = 0x6b018, 2347 .enable_mask = BIT(0), 2348 .hw.init = &(struct clk_init_data){ 2349 .name = "gcc_pcie_0_pipe_clk", 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353}; 2354 2355static struct clk_branch gcc_pcie_0_slv_axi_clk = { 2356 .halt_reg = 0x6b008, 2357 .halt_check = BRANCH_HALT, 2358 .clkr = { 2359 .enable_reg = 0x6b008, 2360 .enable_mask = BIT(0), 2361 .hw.init = &(struct clk_init_data){ 2362 .name = "gcc_pcie_0_slv_axi_clk", 2363 .ops = &clk_branch2_ops, 2364 }, 2365 }, 2366}; 2367 2368static struct clk_branch gcc_pcie_phy_aux_clk = { 2369 .halt_reg = 0x6f004, 2370 .halt_check = BRANCH_HALT, 2371 .clkr = { 2372 .enable_reg = 0x6f004, 2373 .enable_mask = BIT(0), 2374 .hw.init = &(struct clk_init_data){ 2375 .name = "gcc_pcie_phy_aux_clk", 2376 .parent_hws = (const struct clk_hw *[]) { 2377 &pcie_aux_clk_src.clkr.hw, 2378 }, 2379 .num_parents = 1, 2380 .flags = CLK_SET_RATE_PARENT, 2381 .ops = &clk_branch2_ops, 2382 }, 2383 }, 2384}; 2385 2386static struct clk_branch gcc_pdm2_clk = { 2387 .halt_reg = 0x3300c, 2388 .halt_check = BRANCH_HALT, 2389 .clkr = { 2390 .enable_reg = 0x3300c, 2391 .enable_mask = BIT(0), 2392 .hw.init = &(struct clk_init_data){ 2393 .name = "gcc_pdm2_clk", 2394 .parent_hws = (const struct clk_hw *[]) { 2395 &pdm2_clk_src.clkr.hw, 2396 }, 2397 .num_parents = 1, 2398 .flags = CLK_SET_RATE_PARENT, 2399 .ops = &clk_branch2_ops, 2400 }, 2401 }, 2402}; 2403 2404static struct clk_branch gcc_pdm_ahb_clk = { 2405 .halt_reg = 0x33004, 2406 .halt_check = BRANCH_HALT, 2407 .clkr = { 2408 .enable_reg = 0x33004, 2409 .enable_mask = BIT(0), 2410 .hw.init = &(struct clk_init_data){ 2411 .name = "gcc_pdm_ahb_clk", 2412 .ops = &clk_branch2_ops, 2413 }, 2414 }, 2415}; 2416 2417static struct clk_branch gcc_pdm_xo4_clk = { 2418 .halt_reg = 0x33008, 2419 .halt_check = BRANCH_HALT, 2420 .clkr = { 2421 .enable_reg = 0x33008, 2422 .enable_mask = BIT(0), 2423 .hw.init = &(struct clk_init_data){ 2424 .name = "gcc_pdm_xo4_clk", 2425 .ops = &clk_branch2_ops, 2426 }, 2427 }, 2428}; 2429 2430static struct clk_branch gcc_prng_ahb_clk = { 2431 .halt_reg = 0x34004, 2432 .halt_check = BRANCH_HALT_VOTED, 2433 .clkr = { 2434 .enable_reg = 0x52004, 2435 .enable_mask = BIT(13), 2436 .hw.init = &(struct clk_init_data){ 2437 .name = "gcc_prng_ahb_clk", 2438 .ops = &clk_branch2_ops, 2439 }, 2440 }, 2441}; 2442 2443static struct clk_branch gcc_sdcc2_ahb_clk = { 2444 .halt_reg = 0x14008, 2445 .halt_check = BRANCH_HALT, 2446 .clkr = { 2447 .enable_reg = 0x14008, 2448 .enable_mask = BIT(0), 2449 .hw.init = &(struct clk_init_data){ 2450 .name = "gcc_sdcc2_ahb_clk", 2451 .ops = &clk_branch2_ops, 2452 }, 2453 }, 2454}; 2455 2456static struct clk_branch gcc_sdcc2_apps_clk = { 2457 .halt_reg = 0x14004, 2458 .halt_check = BRANCH_HALT, 2459 .clkr = { 2460 .enable_reg = 0x14004, 2461 .enable_mask = BIT(0), 2462 .hw.init = &(struct clk_init_data){ 2463 .name = "gcc_sdcc2_apps_clk", 2464 .parent_hws = (const struct clk_hw *[]) { 2465 &sdcc2_apps_clk_src.clkr.hw, 2466 }, 2467 .num_parents = 1, 2468 .flags = CLK_SET_RATE_PARENT, 2469 .ops = &clk_branch2_ops, 2470 }, 2471 }, 2472}; 2473 2474static struct clk_branch gcc_sdcc4_ahb_clk = { 2475 .halt_reg = 0x16008, 2476 .halt_check = BRANCH_HALT, 2477 .clkr = { 2478 .enable_reg = 0x16008, 2479 .enable_mask = BIT(0), 2480 .hw.init = &(struct clk_init_data){ 2481 .name = "gcc_sdcc4_ahb_clk", 2482 .ops = &clk_branch2_ops, 2483 }, 2484 }, 2485}; 2486 2487static struct clk_branch gcc_sdcc4_apps_clk = { 2488 .halt_reg = 0x16004, 2489 .halt_check = BRANCH_HALT, 2490 .clkr = { 2491 .enable_reg = 0x16004, 2492 .enable_mask = BIT(0), 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "gcc_sdcc4_apps_clk", 2495 .parent_hws = (const struct clk_hw *[]) { 2496 &sdcc4_apps_clk_src.clkr.hw, 2497 }, 2498 .num_parents = 1, 2499 .flags = CLK_SET_RATE_PARENT, 2500 .ops = &clk_branch2_ops, 2501 }, 2502 }, 2503}; 2504 2505static struct clk_branch gcc_tsif_ahb_clk = { 2506 .halt_reg = 0x36004, 2507 .halt_check = BRANCH_HALT, 2508 .clkr = { 2509 .enable_reg = 0x36004, 2510 .enable_mask = BIT(0), 2511 .hw.init = &(struct clk_init_data){ 2512 .name = "gcc_tsif_ahb_clk", 2513 .ops = &clk_branch2_ops, 2514 }, 2515 }, 2516}; 2517 2518static struct clk_branch gcc_tsif_inactivity_timers_clk = { 2519 .halt_reg = 0x3600c, 2520 .halt_check = BRANCH_HALT, 2521 .clkr = { 2522 .enable_reg = 0x3600c, 2523 .enable_mask = BIT(0), 2524 .hw.init = &(struct clk_init_data){ 2525 .name = "gcc_tsif_inactivity_timers_clk", 2526 .ops = &clk_branch2_ops, 2527 }, 2528 }, 2529}; 2530 2531static struct clk_branch gcc_tsif_ref_clk = { 2532 .halt_reg = 0x36008, 2533 .halt_check = BRANCH_HALT, 2534 .clkr = { 2535 .enable_reg = 0x36008, 2536 .enable_mask = BIT(0), 2537 .hw.init = &(struct clk_init_data){ 2538 .name = "gcc_tsif_ref_clk", 2539 .parent_hws = (const struct clk_hw *[]) { 2540 &tsif_ref_clk_src.clkr.hw, 2541 }, 2542 .num_parents = 1, 2543 .flags = CLK_SET_RATE_PARENT, 2544 .ops = &clk_branch2_ops, 2545 }, 2546 }, 2547}; 2548 2549static struct clk_branch gcc_ufs_ahb_clk = { 2550 .halt_reg = 0x7500c, 2551 .halt_check = BRANCH_HALT, 2552 .clkr = { 2553 .enable_reg = 0x7500c, 2554 .enable_mask = BIT(0), 2555 .hw.init = &(struct clk_init_data){ 2556 .name = "gcc_ufs_ahb_clk", 2557 .ops = &clk_branch2_ops, 2558 }, 2559 }, 2560}; 2561 2562static struct clk_branch gcc_ufs_axi_clk = { 2563 .halt_reg = 0x75008, 2564 .halt_check = BRANCH_HALT, 2565 .clkr = { 2566 .enable_reg = 0x75008, 2567 .enable_mask = BIT(0), 2568 .hw.init = &(struct clk_init_data){ 2569 .name = "gcc_ufs_axi_clk", 2570 .parent_hws = (const struct clk_hw *[]) { 2571 &ufs_axi_clk_src.clkr.hw, 2572 }, 2573 .num_parents = 1, 2574 .flags = CLK_SET_RATE_PARENT, 2575 .ops = &clk_branch2_ops, 2576 }, 2577 }, 2578}; 2579 2580static struct clk_branch gcc_ufs_ice_core_clk = { 2581 .halt_reg = 0x7600c, 2582 .halt_check = BRANCH_HALT, 2583 .clkr = { 2584 .enable_reg = 0x7600c, 2585 .enable_mask = BIT(0), 2586 .hw.init = &(struct clk_init_data){ 2587 .name = "gcc_ufs_ice_core_clk", 2588 .ops = &clk_branch2_ops, 2589 }, 2590 }, 2591}; 2592 2593static struct clk_branch gcc_ufs_phy_aux_clk = { 2594 .halt_reg = 0x76040, 2595 .halt_check = BRANCH_HALT, 2596 .clkr = { 2597 .enable_reg = 0x76040, 2598 .enable_mask = BIT(0), 2599 .hw.init = &(struct clk_init_data){ 2600 .name = "gcc_ufs_phy_aux_clk", 2601 .ops = &clk_branch2_ops, 2602 }, 2603 }, 2604}; 2605 2606static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 2607 .halt_reg = 0x75014, 2608 .halt_check = BRANCH_HALT_SKIP, 2609 .clkr = { 2610 .enable_reg = 0x75014, 2611 .enable_mask = BIT(0), 2612 .hw.init = &(struct clk_init_data){ 2613 .name = "gcc_ufs_rx_symbol_0_clk", 2614 .ops = &clk_branch2_ops, 2615 }, 2616 }, 2617}; 2618 2619static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 2620 .halt_reg = 0x7605c, 2621 .halt_check = BRANCH_HALT_SKIP, 2622 .clkr = { 2623 .enable_reg = 0x7605c, 2624 .enable_mask = BIT(0), 2625 .hw.init = &(struct clk_init_data){ 2626 .name = "gcc_ufs_rx_symbol_1_clk", 2627 .ops = &clk_branch2_ops, 2628 }, 2629 }, 2630}; 2631 2632static struct clk_branch gcc_ufs_tx_symbol_0_clk = { 2633 .halt_reg = 0x75010, 2634 .halt_check = BRANCH_HALT_SKIP, 2635 .clkr = { 2636 .enable_reg = 0x75010, 2637 .enable_mask = BIT(0), 2638 .hw.init = &(struct clk_init_data){ 2639 .name = "gcc_ufs_tx_symbol_0_clk", 2640 .ops = &clk_branch2_ops, 2641 }, 2642 }, 2643}; 2644 2645static struct clk_branch gcc_ufs_unipro_core_clk = { 2646 .halt_reg = 0x76008, 2647 .halt_check = BRANCH_HALT, 2648 .clkr = { 2649 .enable_reg = 0x76008, 2650 .enable_mask = BIT(0), 2651 .hw.init = &(struct clk_init_data){ 2652 .name = "gcc_ufs_unipro_core_clk", 2653 .parent_hws = (const struct clk_hw *[]) { 2654 &ufs_unipro_core_clk_src.clkr.hw, 2655 }, 2656 .num_parents = 1, 2657 .flags = CLK_SET_RATE_PARENT, 2658 .ops = &clk_branch2_ops, 2659 }, 2660 }, 2661}; 2662 2663static struct clk_branch gcc_usb30_master_clk = { 2664 .halt_reg = 0xf008, 2665 .halt_check = BRANCH_HALT, 2666 .clkr = { 2667 .enable_reg = 0xf008, 2668 .enable_mask = BIT(0), 2669 .hw.init = &(struct clk_init_data){ 2670 .name = "gcc_usb30_master_clk", 2671 .parent_hws = (const struct clk_hw *[]) { 2672 &usb30_master_clk_src.clkr.hw, 2673 }, 2674 .num_parents = 1, 2675 .flags = CLK_SET_RATE_PARENT, 2676 .ops = &clk_branch2_ops, 2677 }, 2678 }, 2679}; 2680 2681static struct clk_branch gcc_usb30_mock_utmi_clk = { 2682 .halt_reg = 0xf010, 2683 .halt_check = BRANCH_HALT, 2684 .clkr = { 2685 .enable_reg = 0xf010, 2686 .enable_mask = BIT(0), 2687 .hw.init = &(struct clk_init_data){ 2688 .name = "gcc_usb30_mock_utmi_clk", 2689 .parent_hws = (const struct clk_hw *[]) { 2690 &usb30_mock_utmi_clk_src.clkr.hw, 2691 }, 2692 .num_parents = 1, 2693 .flags = CLK_SET_RATE_PARENT, 2694 .ops = &clk_branch2_ops, 2695 }, 2696 }, 2697}; 2698 2699static struct clk_branch gcc_usb30_sleep_clk = { 2700 .halt_reg = 0xf00c, 2701 .halt_check = BRANCH_HALT, 2702 .clkr = { 2703 .enable_reg = 0xf00c, 2704 .enable_mask = BIT(0), 2705 .hw.init = &(struct clk_init_data){ 2706 .name = "gcc_usb30_sleep_clk", 2707 .ops = &clk_branch2_ops, 2708 }, 2709 }, 2710}; 2711 2712static struct clk_branch gcc_usb3_phy_aux_clk = { 2713 .halt_reg = 0x50000, 2714 .halt_check = BRANCH_HALT, 2715 .clkr = { 2716 .enable_reg = 0x50000, 2717 .enable_mask = BIT(0), 2718 .hw.init = &(struct clk_init_data){ 2719 .name = "gcc_usb3_phy_aux_clk", 2720 .parent_hws = (const struct clk_hw *[]) { 2721 &usb3_phy_aux_clk_src.clkr.hw, 2722 }, 2723 .num_parents = 1, 2724 .flags = CLK_SET_RATE_PARENT, 2725 .ops = &clk_branch2_ops, 2726 }, 2727 }, 2728}; 2729 2730static struct clk_branch gcc_usb3_phy_pipe_clk = { 2731 .halt_reg = 0x50004, 2732 .halt_check = BRANCH_HALT_SKIP, 2733 .clkr = { 2734 .enable_reg = 0x50004, 2735 .enable_mask = BIT(0), 2736 .hw.init = &(struct clk_init_data){ 2737 .name = "gcc_usb3_phy_pipe_clk", 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741}; 2742 2743static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 2744 .halt_reg = 0x6a004, 2745 .halt_check = BRANCH_HALT, 2746 .clkr = { 2747 .enable_reg = 0x6a004, 2748 .enable_mask = BIT(0), 2749 .hw.init = &(struct clk_init_data){ 2750 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2751 .ops = &clk_branch2_ops, 2752 }, 2753 }, 2754}; 2755 2756static struct clk_branch gcc_hdmi_clkref_clk = { 2757 .halt_reg = 0x88000, 2758 .clkr = { 2759 .enable_reg = 0x88000, 2760 .enable_mask = BIT(0), 2761 .hw.init = &(struct clk_init_data){ 2762 .name = "gcc_hdmi_clkref_clk", 2763 .parent_data = (const struct clk_parent_data []) { 2764 { .fw_name = "xo" }, 2765 }, 2766 .num_parents = 1, 2767 .ops = &clk_branch2_ops, 2768 }, 2769 }, 2770}; 2771 2772static struct clk_branch gcc_ufs_clkref_clk = { 2773 .halt_reg = 0x88004, 2774 .clkr = { 2775 .enable_reg = 0x88004, 2776 .enable_mask = BIT(0), 2777 .hw.init = &(struct clk_init_data){ 2778 .name = "gcc_ufs_clkref_clk", 2779 .parent_data = (const struct clk_parent_data []) { 2780 { .fw_name = "xo" }, 2781 }, 2782 .num_parents = 1, 2783 .ops = &clk_branch2_ops, 2784 }, 2785 }, 2786}; 2787 2788static struct clk_branch gcc_usb3_clkref_clk = { 2789 .halt_reg = 0x88008, 2790 .clkr = { 2791 .enable_reg = 0x88008, 2792 .enable_mask = BIT(0), 2793 .hw.init = &(struct clk_init_data){ 2794 .name = "gcc_usb3_clkref_clk", 2795 .parent_data = (const struct clk_parent_data []) { 2796 { .fw_name = "xo" }, 2797 }, 2798 .num_parents = 1, 2799 .ops = &clk_branch2_ops, 2800 }, 2801 }, 2802}; 2803 2804static struct clk_branch gcc_pcie_clkref_clk = { 2805 .halt_reg = 0x8800c, 2806 .clkr = { 2807 .enable_reg = 0x8800c, 2808 .enable_mask = BIT(0), 2809 .hw.init = &(struct clk_init_data){ 2810 .name = "gcc_pcie_clkref_clk", 2811 .parent_data = (const struct clk_parent_data []) { 2812 { .fw_name = "xo" }, 2813 }, 2814 .num_parents = 1, 2815 .ops = &clk_branch2_ops, 2816 }, 2817 }, 2818}; 2819 2820static struct clk_branch gcc_rx1_usb2_clkref_clk = { 2821 .halt_reg = 0x88014, 2822 .clkr = { 2823 .enable_reg = 0x88014, 2824 .enable_mask = BIT(0), 2825 .hw.init = &(struct clk_init_data){ 2826 .name = "gcc_rx1_usb2_clkref_clk", 2827 .parent_data = (const struct clk_parent_data []) { 2828 { .fw_name = "xo" }, 2829 }, 2830 .num_parents = 1, 2831 .ops = &clk_branch2_ops, 2832 }, 2833 }, 2834}; 2835 2836static struct clk_branch gcc_im_sleep_clk = { 2837 .halt_reg = 0x4300c, 2838 .halt_check = BRANCH_HALT, 2839 .clkr = { 2840 .enable_reg = 0x4300c, 2841 .enable_mask = BIT(0), 2842 .hw.init = &(const struct clk_init_data){ 2843 .name = "gcc_im_sleep_clk", 2844 .ops = &clk_branch2_ops, 2845 }, 2846 }, 2847}; 2848 2849static struct clk_branch aggre2_snoc_north_axi_clk = { 2850 .halt_reg = 0x83010, 2851 .halt_check = BRANCH_HALT, 2852 .clkr = { 2853 .enable_reg = 0x83010, 2854 .enable_mask = BIT(0), 2855 .hw.init = &(const struct clk_init_data){ 2856 .name = "aggre2_snoc_north_axi_clk", 2857 .ops = &clk_branch2_ops, 2858 }, 2859 }, 2860}; 2861 2862static struct clk_branch ssc_xo_clk = { 2863 .halt_reg = 0x63018, 2864 .halt_check = BRANCH_HALT, 2865 .clkr = { 2866 .enable_reg = 0x63018, 2867 .enable_mask = BIT(0), 2868 .hw.init = &(const struct clk_init_data){ 2869 .name = "ssc_xo_clk", 2870 .ops = &clk_branch2_ops, 2871 }, 2872 }, 2873}; 2874 2875static struct clk_branch ssc_cnoc_ahbs_clk = { 2876 .halt_reg = 0x6300c, 2877 .halt_check = BRANCH_HALT, 2878 .clkr = { 2879 .enable_reg = 0x6300c, 2880 .enable_mask = BIT(0), 2881 .hw.init = &(const struct clk_init_data){ 2882 .name = "ssc_cnoc_ahbs_clk", 2883 .ops = &clk_branch2_ops, 2884 }, 2885 }, 2886}; 2887 2888static struct gdsc pcie_0_gdsc = { 2889 .gdscr = 0x6b004, 2890 .gds_hw_ctrl = 0x0, 2891 .pd = { 2892 .name = "pcie_0_gdsc", 2893 }, 2894 .pwrsts = PWRSTS_OFF_ON, 2895 .flags = VOTABLE, 2896}; 2897 2898static struct gdsc ufs_gdsc = { 2899 .gdscr = 0x75004, 2900 .gds_hw_ctrl = 0x0, 2901 .pd = { 2902 .name = "ufs_gdsc", 2903 }, 2904 .pwrsts = PWRSTS_OFF_ON, 2905 .flags = VOTABLE, 2906}; 2907 2908static struct gdsc usb_30_gdsc = { 2909 .gdscr = 0xf004, 2910 .gds_hw_ctrl = 0x0, 2911 .pd = { 2912 .name = "usb_30_gdsc", 2913 }, 2914 .pwrsts = PWRSTS_OFF_ON, 2915 .flags = VOTABLE, 2916}; 2917 2918static struct clk_regmap *gcc_msm8998_clocks[] = { 2919 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2920 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2921 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2922 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2923 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2924 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2925 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2926 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2927 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2928 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2929 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2930 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2931 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2932 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2933 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2934 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2935 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2936 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2937 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2938 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2939 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2940 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2941 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2942 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2943 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2944 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2945 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2946 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2947 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2948 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2949 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr, 2950 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr, 2951 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr, 2952 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr, 2953 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr, 2954 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, 2955 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, 2956 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2957 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2958 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2959 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2960 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2961 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2962 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2963 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2964 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2965 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2966 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2967 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2968 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2969 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 2970 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2971 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2972 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2973 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2974 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2975 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2976 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2977 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2978 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2979 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2980 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2981 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2982 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2983 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2984 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2985 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2986 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr, 2987 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2988 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2989 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2990 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, 2991 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2992 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2993 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2994 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 2995 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, 2996 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, 2997 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, 2998 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, 2999 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, 3000 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr, 3001 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, 3002 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr, 3003 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 3004 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr, 3005 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr, 3006 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, 3007 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr, 3008 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3009 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3010 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3011 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3012 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3013 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, 3014 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3015 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3016 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3017 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3018 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3019 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3020 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3021 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3022 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 3023 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 3024 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 3025 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, 3026 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, 3027 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, 3028 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, 3029 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, 3030 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, 3031 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, 3032 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, 3033 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 3034 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 3035 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 3036 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 3037 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 3038 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 3039 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3040 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3041 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3042 [GPLL0] = &gpll0.clkr, 3043 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, 3044 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr, 3045 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr, 3046 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr, 3047 [GPLL1] = &gpll1.clkr, 3048 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr, 3049 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr, 3050 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr, 3051 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr, 3052 [GPLL2] = &gpll2.clkr, 3053 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr, 3054 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, 3055 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr, 3056 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr, 3057 [GPLL3] = &gpll3.clkr, 3058 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, 3059 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr, 3060 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr, 3061 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr, 3062 [GPLL4] = &gpll4.clkr, 3063 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, 3064 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr, 3065 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr, 3066 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr, 3067 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, 3068 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, 3069 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, 3070 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3071 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3072 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 3073 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 3074 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, 3075 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, 3076 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 3077 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 3078 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, 3079 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr, 3080 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, 3081 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, 3082 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, 3083 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, 3084 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3085 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3086 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, 3087 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, 3088 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, 3089 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, 3090 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, 3091 [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr, 3092 [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, 3093 [SSC_XO] = &ssc_xo_clk.clkr, 3094 [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, 3095}; 3096 3097static struct gdsc *gcc_msm8998_gdscs[] = { 3098 [PCIE_0_GDSC] = &pcie_0_gdsc, 3099 [UFS_GDSC] = &ufs_gdsc, 3100 [USB_30_GDSC] = &usb_30_gdsc, 3101}; 3102 3103static const struct qcom_reset_map gcc_msm8998_resets[] = { 3104 [GCC_BLSP1_QUP1_BCR] = { 0x19000 }, 3105 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 }, 3106 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 }, 3107 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 }, 3108 [GCC_BLSP1_QUP5_BCR] = { 0x21000 }, 3109 [GCC_BLSP1_QUP6_BCR] = { 0x23000 }, 3110 [GCC_BLSP2_QUP1_BCR] = { 0x26000 }, 3111 [GCC_BLSP2_QUP2_BCR] = { 0x28000 }, 3112 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 }, 3113 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 }, 3114 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 }, 3115 [GCC_BLSP2_QUP6_BCR] = { 0x30000 }, 3116 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3117 [GCC_PDM_BCR] = { 0x33000 }, 3118 [GCC_SDCC2_BCR] = { 0x14000 }, 3119 [GCC_SDCC4_BCR] = { 0x16000 }, 3120 [GCC_TSIF_BCR] = { 0x36000 }, 3121 [GCC_UFS_BCR] = { 0x75000 }, 3122 [GCC_USB_30_BCR] = { 0xf000 }, 3123 [GCC_SYSTEM_NOC_BCR] = { 0x4000 }, 3124 [GCC_CONFIG_NOC_BCR] = { 0x5000 }, 3125 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 }, 3126 [GCC_IMEM_BCR] = { 0x8000 }, 3127 [GCC_PIMEM_BCR] = { 0xa000 }, 3128 [GCC_MMSS_BCR] = { 0xb000 }, 3129 [GCC_QDSS_BCR] = { 0xc000 }, 3130 [GCC_WCSS_BCR] = { 0x11000 }, 3131 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3132 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3133 [GCC_BLSP1_BCR] = { 0x17000 }, 3134 [GCC_BLSP1_UART1_BCR] = { 0x1a000 }, 3135 [GCC_BLSP1_UART2_BCR] = { 0x1c000 }, 3136 [GCC_BLSP1_UART3_BCR] = { 0x1e000 }, 3137 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 }, 3138 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 }, 3139 [GCC_BLSP2_BCR] = { 0x25000 }, 3140 [GCC_BLSP2_UART1_BCR] = { 0x27000 }, 3141 [GCC_BLSP2_UART2_BCR] = { 0x29000 }, 3142 [GCC_BLSP2_UART3_BCR] = { 0x2b000 }, 3143 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 }, 3144 [GCC_PRNG_BCR] = { 0x34000 }, 3145 [GCC_TSIF_0_RESET] = { 0x36024 }, 3146 [GCC_TSIF_1_RESET] = { 0x36028 }, 3147 [GCC_TCSR_BCR] = { 0x37000 }, 3148 [GCC_BOOT_ROM_BCR] = { 0x38000 }, 3149 [GCC_MSG_RAM_BCR] = { 0x39000 }, 3150 [GCC_TLMM_BCR] = { 0x3a000 }, 3151 [GCC_MPM_BCR] = { 0x3b000 }, 3152 [GCC_SEC_CTRL_BCR] = { 0x3d000 }, 3153 [GCC_SPMI_BCR] = { 0x3f000 }, 3154 [GCC_SPDM_BCR] = { 0x40000 }, 3155 [GCC_CE1_BCR] = { 0x41000 }, 3156 [GCC_BIMC_BCR] = { 0x44000 }, 3157 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 }, 3158 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 }, 3159 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 }, 3160 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 }, 3161 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 }, 3162 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 }, 3163 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c }, 3164 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 }, 3165 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 }, 3166 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 }, 3167 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 }, 3168 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 }, 3169 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 }, 3170 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 }, 3171 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 }, 3172 [GCC_APB2JTAG_BCR] = { 0x4c000 }, 3173 [GCC_RBCPR_CX_BCR] = { 0x4e000 }, 3174 [GCC_RBCPR_MX_BCR] = { 0x4f000 }, 3175 [GCC_USB3_PHY_BCR] = { 0x50020 }, 3176 [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, 3177 [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, 3178 [GCC_SSC_BCR] = { 0x63000 }, 3179 [GCC_SSC_RESET] = { 0x63020 }, 3180 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 3181 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3182 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3183 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3184 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3185 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c }, 3186 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 }, 3187 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 }, 3188 [GCC_GPU_BCR] = { 0x71000 }, 3189 [GCC_SPSS_BCR] = { 0x72000 }, 3190 [GCC_OBT_ODT_BCR] = { 0x73000 }, 3191 [GCC_MSS_RESTART] = { 0x79000 }, 3192 [GCC_VS_BCR] = { 0x7a000 }, 3193 [GCC_MSS_VS_RESET] = { 0x7a100 }, 3194 [GCC_GPU_VS_RESET] = { 0x7a104 }, 3195 [GCC_APC0_VS_RESET] = { 0x7a108 }, 3196 [GCC_APC1_VS_RESET] = { 0x7a10c }, 3197 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 }, 3198 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 }, 3199 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 }, 3200 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 }, 3201 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 }, 3202 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 }, 3203 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 }, 3204 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 }, 3205 [GCC_AGGRE1_NOC_BCR] = { 0x82000 }, 3206 [GCC_AGGRE2_NOC_BCR] = { 0x83000 }, 3207 [GCC_DCC_BCR] = { 0x84000 }, 3208 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 }, 3209 [GCC_IPA_BCR] = { 0x89000 }, 3210 [GCC_GLM_BCR] = { 0x8b000 }, 3211 [GCC_SKL_BCR] = { 0x8c000 }, 3212 [GCC_MSMPU_BCR] = { 0x8d000 }, 3213}; 3214 3215static const struct regmap_config gcc_msm8998_regmap_config = { 3216 .reg_bits = 32, 3217 .reg_stride = 4, 3218 .val_bits = 32, 3219 .max_register = 0x8f000, 3220 .fast_io = true, 3221}; 3222 3223static const struct qcom_cc_desc gcc_msm8998_desc = { 3224 .config = &gcc_msm8998_regmap_config, 3225 .clks = gcc_msm8998_clocks, 3226 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks), 3227 .resets = gcc_msm8998_resets, 3228 .num_resets = ARRAY_SIZE(gcc_msm8998_resets), 3229 .gdscs = gcc_msm8998_gdscs, 3230 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs), 3231}; 3232 3233static int gcc_msm8998_probe(struct platform_device *pdev) 3234{ 3235 struct regmap *regmap; 3236 int ret; 3237 3238 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc); 3239 if (IS_ERR(regmap)) 3240 return PTR_ERR(regmap); 3241 3242 /* 3243 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be 3244 * turned off by hardware during certain apps low power modes. 3245 */ 3246 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); 3247 if (ret) 3248 return ret; 3249 3250 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); 3251} 3252 3253static const struct of_device_id gcc_msm8998_match_table[] = { 3254 { .compatible = "qcom,gcc-msm8998" }, 3255 { } 3256}; 3257MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table); 3258 3259static struct platform_driver gcc_msm8998_driver = { 3260 .probe = gcc_msm8998_probe, 3261 .driver = { 3262 .name = "gcc-msm8998", 3263 .of_match_table = gcc_msm8998_match_table, 3264 }, 3265}; 3266 3267static int __init gcc_msm8998_init(void) 3268{ 3269 return platform_driver_register(&gcc_msm8998_driver); 3270} 3271core_initcall(gcc_msm8998_init); 3272 3273static void __exit gcc_msm8998_exit(void) 3274{ 3275 platform_driver_unregister(&gcc_msm8998_driver); 3276} 3277module_exit(gcc_msm8998_exit); 3278 3279MODULE_DESCRIPTION("QCOM GCC msm8998 Driver"); 3280MODULE_LICENSE("GPL v2"); 3281MODULE_ALIAS("platform:gcc-msm8998");