cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mss-sc7180.c (2861B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
      4 */
      5
      6#include <linux/clk-provider.h>
      7#include <linux/platform_device.h>
      8#include <linux/module.h>
      9#include <linux/pm_clock.h>
     10#include <linux/pm_runtime.h>
     11#include <linux/regmap.h>
     12
     13#include <dt-bindings/clock/qcom,mss-sc7180.h>
     14
     15#include "clk-regmap.h"
     16#include "clk-branch.h"
     17#include "common.h"
     18
     19static struct clk_branch mss_axi_nav_clk = {
     20	.halt_reg = 0x20bc,
     21	.halt_check = BRANCH_HALT,
     22	.clkr = {
     23		.enable_reg = 0x20bc,
     24		.enable_mask = BIT(0),
     25		.hw.init = &(struct clk_init_data){
     26			.name = "mss_axi_nav_clk",
     27			.parent_data = &(const struct clk_parent_data){
     28				.fw_name = "gcc_mss_nav_axi",
     29			},
     30			.num_parents = 1,
     31			.ops = &clk_branch2_ops,
     32		},
     33	},
     34};
     35
     36static struct clk_branch mss_axi_crypto_clk = {
     37	.halt_reg = 0x20cc,
     38	.halt_check = BRANCH_HALT,
     39	.clkr = {
     40		.enable_reg = 0x20cc,
     41		.enable_mask = BIT(0),
     42		.hw.init = &(struct clk_init_data){
     43			.name = "mss_axi_crypto_clk",
     44			.parent_data = &(const struct clk_parent_data){
     45				.fw_name = "gcc_mss_mfab_axis",
     46			},
     47			.num_parents = 1,
     48			.ops = &clk_branch2_ops,
     49		},
     50	},
     51};
     52
     53static const struct regmap_config mss_regmap_config = {
     54	.reg_bits	= 32,
     55	.reg_stride	= 4,
     56	.val_bits	= 32,
     57	.fast_io	= true,
     58	.max_register	= 0x41aa0cc,
     59};
     60
     61static struct clk_regmap *mss_sc7180_clocks[] = {
     62	[MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr,
     63	[MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr,
     64};
     65
     66static const struct qcom_cc_desc mss_sc7180_desc = {
     67	.config = &mss_regmap_config,
     68	.clks = mss_sc7180_clocks,
     69	.num_clks = ARRAY_SIZE(mss_sc7180_clocks),
     70};
     71
     72static int mss_sc7180_probe(struct platform_device *pdev)
     73{
     74	int ret;
     75
     76	ret = devm_pm_runtime_enable(&pdev->dev);
     77	if (ret)
     78		return ret;
     79
     80	ret = devm_pm_clk_create(&pdev->dev);
     81	if (ret)
     82		return ret;
     83
     84	ret = pm_clk_add(&pdev->dev, "cfg_ahb");
     85	if (ret < 0) {
     86		dev_err(&pdev->dev, "failed to acquire iface clock\n");
     87		return ret;
     88	}
     89
     90	ret = qcom_cc_probe(pdev, &mss_sc7180_desc);
     91	if (ret < 0)
     92		return ret;
     93
     94	return 0;
     95}
     96
     97static const struct dev_pm_ops mss_sc7180_pm_ops = {
     98	SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
     99};
    100
    101static const struct of_device_id mss_sc7180_match_table[] = {
    102	{ .compatible = "qcom,sc7180-mss" },
    103	{ }
    104};
    105MODULE_DEVICE_TABLE(of, mss_sc7180_match_table);
    106
    107static struct platform_driver mss_sc7180_driver = {
    108	.probe		= mss_sc7180_probe,
    109	.driver		= {
    110		.name		= "sc7180-mss",
    111		.of_match_table = mss_sc7180_match_table,
    112		.pm = &mss_sc7180_pm_ops,
    113	},
    114};
    115
    116static int __init mss_sc7180_init(void)
    117{
    118	return platform_driver_register(&mss_sc7180_driver);
    119}
    120subsys_initcall(mss_sc7180_init);
    121
    122static void __exit mss_sc7180_exit(void)
    123{
    124	platform_driver_unregister(&mss_sc7180_driver);
    125}
    126module_exit(mss_sc7180_exit);
    127
    128MODULE_DESCRIPTION("QTI MSS SC7180 Driver");
    129MODULE_LICENSE("GPL v2");