r9a07g043-cpg.c (11369B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * RZ/G2UL CPG driver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/device.h> 10#include <linux/init.h> 11#include <linux/kernel.h> 12 13#include <dt-bindings/clock/r9a07g043-cpg.h> 14 15#include "rzg2l-cpg.h" 16 17enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, 20 21 /* External Input Clocks */ 22 CLK_EXTAL, 23 24 /* Internal Core Clocks */ 25 CLK_OSC_DIV1000, 26 CLK_PLL1, 27 CLK_PLL2, 28 CLK_PLL2_DIV2, 29 CLK_PLL2_DIV2_8, 30 CLK_PLL2_DIV2_10, 31 CLK_PLL3, 32 CLK_PLL3_400, 33 CLK_PLL3_533, 34 CLK_PLL3_DIV2, 35 CLK_PLL3_DIV2_4, 36 CLK_PLL3_DIV2_4_2, 37 CLK_SEL_PLL3_3, 38 CLK_DIV_PLL3_C, 39 CLK_PLL5, 40 CLK_PLL5_500, 41 CLK_PLL5_250, 42 CLK_PLL6, 43 CLK_PLL6_250, 44 CLK_P1_DIV2, 45 CLK_PLL2_800, 46 CLK_PLL2_SDHI_533, 47 CLK_PLL2_SDHI_400, 48 CLK_PLL2_SDHI_266, 49 CLK_SD0_DIV4, 50 CLK_SD1_DIV4, 51 52 /* Module Clocks */ 53 MOD_CLK_BASE, 54}; 55 56/* Divider tables */ 57static const struct clk_div_table dtable_1_8[] = { 58 {0, 1}, 59 {1, 2}, 60 {2, 4}, 61 {3, 8}, 62 {0, 0}, 63}; 64 65static const struct clk_div_table dtable_1_32[] = { 66 {0, 1}, 67 {1, 2}, 68 {2, 4}, 69 {3, 8}, 70 {4, 32}, 71 {0, 0}, 72}; 73 74/* Mux clock tables */ 75static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 76static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 77static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 78 79static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 80 /* External Clock Inputs */ 81 DEF_INPUT("extal", CLK_EXTAL), 82 83 /* Internal Core Clocks */ 84 DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), 85 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 86 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 87 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 88 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 89 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 90 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), 91 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), 92 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), 93 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 94 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), 95 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 96 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 97 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 98 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 99 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), 100 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), 101 DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), 102 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), 103 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 104 DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), 105 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), 106 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 107 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 108 109 /* Core output clk */ 110 DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), 111 DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), 112 DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), 113 DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), 114 DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), 115 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), 116 DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), 117 DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 118 DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 119 DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), 120 DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 121 DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 122 DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi), 123 DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi), 124 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), 125 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), 126}; 127 128static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 129 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 130 0x514, 0), 131 DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 132 0x518, 0), 133 DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 134 0x518, 1), 135 DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 136 0x52c, 0), 137 DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 138 0x52c, 1), 139 DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, 140 0x534, 0), 141 DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, 142 0x534, 1), 143 DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 144 0x534, 2), 145 DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 146 0x548, 0), 147 DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 148 0x548, 1), 149 DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0, 150 0x548, 4), 151 DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, 152 0x548, 5), 153 DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, 154 0x550, 0), 155 DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, 156 0x550, 1), 157 DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 158 0x554, 0), 159 DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, 160 0x554, 1), 161 DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, 162 0x554, 2), 163 DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, 164 0x554, 3), 165 DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, 166 0x554, 4), 167 DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, 168 0x554, 5), 169 DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, 170 0x554, 6), 171 DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 172 0x554, 7), 173 DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, 174 0x570, 0), 175 DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, 176 0x570, 1), 177 DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, 178 0x570, 2), 179 DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, 180 0x570, 3), 181 DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, 182 0x570, 4), 183 DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, 184 0x570, 5), 185 DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, 186 0x570, 6), 187 DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 188 0x570, 7), 189 DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, 190 0x578, 0), 191 DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, 192 0x578, 1), 193 DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, 194 0x578, 2), 195 DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1, 196 0x578, 3), 197 DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 198 0x57c, 0), 199 DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, 200 0x57c, 0), 201 DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, 202 0x57c, 1), 203 DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 204 0x57c, 1), 205 DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, 206 0x580, 0), 207 DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, 208 0x580, 1), 209 DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, 210 0x580, 2), 211 DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, 212 0x580, 3), 213 DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 214 0x584, 0), 215 DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, 216 0x584, 1), 217 DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, 218 0x584, 2), 219 DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, 220 0x584, 3), 221 DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, 222 0x584, 4), 223 DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, 224 0x588, 0), 225 DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 226 0x588, 1), 227 DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0, 228 0x590, 0), 229 DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0, 230 0x590, 1), 231 DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0, 232 0x590, 2), 233 DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, 234 0x594, 0), 235 DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 236 0x598, 0), 237 DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, 238 0x5a8, 0), 239 DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, 240 0x5a8, 1), 241 DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 242 0x5ac, 0), 243}; 244 245static struct rzg2l_reset r9a07g043_resets[] = { 246 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), 247 DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), 248 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), 249 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), 250 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), 251 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), 252 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), 253 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), 254 DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), 255 DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), 256 DEF_RST(R9A07G043_SPI_RST, 0x850, 0), 257 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 258 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 259 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), 260 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), 261 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), 262 DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), 263 DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0), 264 DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1), 265 DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2), 266 DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3), 267 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), 268 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), 269 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), 270 DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), 271 DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), 272 DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), 273 DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), 274 DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), 275 DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), 276 DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), 277 DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), 278 DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), 279 DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), 280 DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0), 281 DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1), 282 DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2), 283 DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0), 284 DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1), 285 DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), 286 DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), 287 DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), 288 DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), 289 DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), 290 DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), 291}; 292 293static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 294 MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, 295 MOD_CLK_BASE + R9A07G043_IA55_CLK, 296 MOD_CLK_BASE + R9A07G043_DMAC_ACLK, 297}; 298 299const struct rzg2l_cpg_info r9a07g043_cpg_info = { 300 /* Core Clocks */ 301 .core_clks = r9a07g043_core_clks, 302 .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), 303 .last_dt_core_clk = LAST_DT_CORE_CLK, 304 .num_total_core_clks = MOD_CLK_BASE, 305 306 /* Critical Module Clocks */ 307 .crit_mod_clks = r9a07g043_crit_mod_clks, 308 .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), 309 310 /* Module Clocks */ 311 .mod_clks = r9a07g043_mod_clks, 312 .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), 313 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, 314 315 /* Resets */ 316 .resets = r9a07g043_resets, 317 .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ 318 319 .has_clk_mon_regs = true, 320};