cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rcar-gen4-cpg.h (2127B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * R-Car Gen4 Clock Pulse Generator
      4 *
      5 * Copyright (C) 2021 Renesas Electronics Corp.
      6 *
      7 */
      8
      9#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
     10#define __CLK_RENESAS_RCAR_GEN4_CPG_H__
     11
     12enum rcar_gen4_clk_types {
     13	CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
     14	CLK_TYPE_GEN4_PLL1,
     15	CLK_TYPE_GEN4_PLL2,
     16	CLK_TYPE_GEN4_PLL2X_3X,	/* r8a779a0 only */
     17	CLK_TYPE_GEN4_PLL3,
     18	CLK_TYPE_GEN4_PLL5,
     19	CLK_TYPE_GEN4_PLL4,
     20	CLK_TYPE_GEN4_PLL6,
     21	CLK_TYPE_GEN4_SDSRC,
     22	CLK_TYPE_GEN4_SDH,
     23	CLK_TYPE_GEN4_SD,
     24	CLK_TYPE_GEN4_MDSEL,	/* Select parent/divider using mode pin */
     25	CLK_TYPE_GEN4_Z,
     26	CLK_TYPE_GEN4_OSC,	/* OSC EXTAL predivider and fixed divider */
     27	CLK_TYPE_GEN4_RPCSRC,
     28	CLK_TYPE_GEN4_RPC,
     29	CLK_TYPE_GEN4_RPCD2,
     30
     31	/* SoC specific definitions start here */
     32	CLK_TYPE_GEN4_SOC_BASE,
     33};
     34
     35#define DEF_GEN4_SDH(_name, _id, _parent, _offset)	\
     36	DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
     37
     38#define DEF_GEN4_SD(_name, _id, _parent, _offset)	\
     39	DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
     40
     41#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
     42	DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL,	\
     43		 (_parent0) << 16 | (_parent1),		\
     44		 .div = (_div0) << 16 | (_div1), .offset = _md)
     45
     46#define DEF_GEN4_OSC(_name, _id, _parent, _div)		\
     47	DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
     48
     49#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset)	\
     50	DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
     51
     52struct rcar_gen4_cpg_pll_config {
     53	u8 extal_div;
     54	u8 pll1_mult;
     55	u8 pll1_div;
     56	u8 pll2_mult;
     57	u8 pll2_div;
     58	u8 pll3_mult;
     59	u8 pll3_div;
     60	u8 pll4_mult;
     61	u8 pll4_div;
     62	u8 pll5_mult;
     63	u8 pll5_div;
     64	u8 pll6_mult;
     65	u8 pll6_div;
     66	u8 osc_prediv;
     67};
     68
     69#define CPG_RPCCKCR	0x874
     70#define SD0CKCR1	0x8a4
     71
     72struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
     73	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
     74	struct clk **clks, void __iomem *base,
     75	struct raw_notifier_head *notifiers);
     76int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
     77		       unsigned int clk_extalr, u32 mode);
     78
     79#endif