cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-cpu.c (10865B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (c) 2014 MundoReader S.L.
      4 * Author: Heiko Stuebner <heiko@sntech.de>
      5 *
      6 * based on clk/samsung/clk-cpu.c
      7 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
      8 * Author: Thomas Abraham <thomas.ab@samsung.com>
      9 *
     10 * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs.
     11 * The CPU clock is typically derived from a hierarchy of clock
     12 * blocks which includes mux and divider blocks. There are a number of other
     13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
     14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
     15 * CPU clock rate and this relation is usually specified in the hardware manual
     16 * of the SoC or supplied after the SoC characterization.
     17 *
     18 * The below implementation of the CPU clock allows the rate changes of the CPU
     19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
     20 * domain. The platform clock driver provides a clock register configuration
     21 * for each configurable rate which is then used to program the clock hardware
     22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
     23 * clocks.
     24 *
     25 * On a rate change request for the CPU clock, the rate change is propagated
     26 * upto the PLL supplying the clock to the CPU domain clock blocks. While the
     27 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
     28 * alternate clock source. If required, the alternate clock source is divided
     29 * down in order to keep the output clock rate within the previous OPP limits.
     30 */
     31
     32#include <linux/of.h>
     33#include <linux/slab.h>
     34#include <linux/io.h>
     35#include <linux/clk.h>
     36#include <linux/clk-provider.h>
     37#include "clk.h"
     38
     39/**
     40 * struct rockchip_cpuclk: information about clock supplied to a CPU core.
     41 * @hw:		handle between ccf and cpu clock.
     42 * @alt_parent:	alternate parent clock to use when switching the speed
     43 *		of the primary parent clock.
     44 * @reg_base:	base register for cpu-clock values.
     45 * @clk_nb:	clock notifier registered for changes in clock speed of the
     46 *		primary parent clock.
     47 * @rate_count:	number of rates in the rate_table
     48 * @rate_table:	pll-rates and their associated dividers
     49 * @reg_data:	cpu-specific register settings
     50 * @lock:	clock lock
     51 */
     52struct rockchip_cpuclk {
     53	struct clk_hw				hw;
     54	struct clk				*alt_parent;
     55	void __iomem				*reg_base;
     56	struct notifier_block			clk_nb;
     57	unsigned int				rate_count;
     58	struct rockchip_cpuclk_rate_table	*rate_table;
     59	const struct rockchip_cpuclk_reg_data	*reg_data;
     60	spinlock_t				*lock;
     61};
     62
     63#define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw)
     64#define to_rockchip_cpuclk_nb(nb) \
     65			container_of(nb, struct rockchip_cpuclk, clk_nb)
     66
     67static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings(
     68			    struct rockchip_cpuclk *cpuclk, unsigned long rate)
     69{
     70	const struct rockchip_cpuclk_rate_table *rate_table =
     71							cpuclk->rate_table;
     72	int i;
     73
     74	for (i = 0; i < cpuclk->rate_count; i++) {
     75		if (rate == rate_table[i].prate)
     76			return &rate_table[i];
     77	}
     78
     79	return NULL;
     80}
     81
     82static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,
     83					unsigned long parent_rate)
     84{
     85	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
     86	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
     87	u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
     88
     89	clksel0 >>= reg_data->div_core_shift[0];
     90	clksel0 &= reg_data->div_core_mask[0];
     91	return parent_rate / (clksel0 + 1);
     92}
     93
     94static const struct clk_ops rockchip_cpuclk_ops = {
     95	.recalc_rate = rockchip_cpuclk_recalc_rate,
     96};
     97
     98static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
     99				const struct rockchip_cpuclk_rate_table *rate)
    100{
    101	int i;
    102
    103	/* alternate parent is active now. set the dividers */
    104	for (i = 0; i < ARRAY_SIZE(rate->divs); i++) {
    105		const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i];
    106
    107		if (!clksel->reg)
    108			continue;
    109
    110		pr_debug("%s: setting reg 0x%x to 0x%x\n",
    111			 __func__, clksel->reg, clksel->val);
    112		writel(clksel->val, cpuclk->reg_base + clksel->reg);
    113	}
    114}
    115
    116static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
    117					   struct clk_notifier_data *ndata)
    118{
    119	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
    120	const struct rockchip_cpuclk_rate_table *rate;
    121	unsigned long alt_prate, alt_div;
    122	unsigned long flags;
    123	int i = 0;
    124
    125	/* check validity of the new rate */
    126	rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
    127	if (!rate) {
    128		pr_err("%s: Invalid rate : %lu for cpuclk\n",
    129		       __func__, ndata->new_rate);
    130		return -EINVAL;
    131	}
    132
    133	alt_prate = clk_get_rate(cpuclk->alt_parent);
    134
    135	spin_lock_irqsave(cpuclk->lock, flags);
    136
    137	/*
    138	 * If the old parent clock speed is less than the clock speed
    139	 * of the alternate parent, then it should be ensured that at no point
    140	 * the armclk speed is more than the old_rate until the dividers are
    141	 * set.
    142	 */
    143	if (alt_prate > ndata->old_rate) {
    144		/* calculate dividers */
    145		alt_div =  DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
    146		if (alt_div > reg_data->div_core_mask[0]) {
    147			pr_warn("%s: limiting alt-divider %lu to %d\n",
    148				__func__, alt_div, reg_data->div_core_mask[0]);
    149			alt_div = reg_data->div_core_mask[0];
    150		}
    151
    152		/*
    153		 * Change parents and add dividers in a single transaction.
    154		 *
    155		 * NOTE: we do this in a single transaction so we're never
    156		 * dividing the primary parent by the extra dividers that were
    157		 * needed for the alt.
    158		 */
    159		pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
    160			 __func__, alt_div, alt_prate, ndata->old_rate);
    161
    162		for (i = 0; i < reg_data->num_cores; i++) {
    163			writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
    164					     reg_data->div_core_shift[i]),
    165			       cpuclk->reg_base + reg_data->core_reg[i]);
    166		}
    167	}
    168	/* select alternate parent */
    169	writel(HIWORD_UPDATE(reg_data->mux_core_alt,
    170			     reg_data->mux_core_mask,
    171			     reg_data->mux_core_shift),
    172	       cpuclk->reg_base + reg_data->core_reg[0]);
    173
    174	spin_unlock_irqrestore(cpuclk->lock, flags);
    175	return 0;
    176}
    177
    178static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
    179					    struct clk_notifier_data *ndata)
    180{
    181	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
    182	const struct rockchip_cpuclk_rate_table *rate;
    183	unsigned long flags;
    184	int i = 0;
    185
    186	rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
    187	if (!rate) {
    188		pr_err("%s: Invalid rate : %lu for cpuclk\n",
    189		       __func__, ndata->new_rate);
    190		return -EINVAL;
    191	}
    192
    193	spin_lock_irqsave(cpuclk->lock, flags);
    194
    195	if (ndata->old_rate < ndata->new_rate)
    196		rockchip_cpuclk_set_dividers(cpuclk, rate);
    197
    198	/*
    199	 * post-rate change event, re-mux to primary parent and remove dividers.
    200	 *
    201	 * NOTE: we do this in a single transaction so we're never dividing the
    202	 * primary parent by the extra dividers that were needed for the alt.
    203	 */
    204
    205	writel(HIWORD_UPDATE(reg_data->mux_core_main,
    206			     reg_data->mux_core_mask,
    207			     reg_data->mux_core_shift),
    208	       cpuclk->reg_base + reg_data->core_reg[0]);
    209
    210	/* remove dividers */
    211	for (i = 0; i < reg_data->num_cores; i++) {
    212		writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
    213				     reg_data->div_core_shift[i]),
    214		       cpuclk->reg_base + reg_data->core_reg[i]);
    215	}
    216
    217	if (ndata->old_rate > ndata->new_rate)
    218		rockchip_cpuclk_set_dividers(cpuclk, rate);
    219
    220	spin_unlock_irqrestore(cpuclk->lock, flags);
    221	return 0;
    222}
    223
    224/*
    225 * This clock notifier is called when the frequency of the parent clock
    226 * of cpuclk is to be changed. This notifier handles the setting up all
    227 * the divider clocks, remux to temporary parent and handling the safe
    228 * frequency levels when using temporary parent.
    229 */
    230static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb,
    231					unsigned long event, void *data)
    232{
    233	struct clk_notifier_data *ndata = data;
    234	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
    235	int ret = 0;
    236
    237	pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
    238		 __func__, event, ndata->old_rate, ndata->new_rate);
    239	if (event == PRE_RATE_CHANGE)
    240		ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);
    241	else if (event == POST_RATE_CHANGE)
    242		ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);
    243
    244	return notifier_from_errno(ret);
    245}
    246
    247struct clk *rockchip_clk_register_cpuclk(const char *name,
    248			const char *const *parent_names, u8 num_parents,
    249			const struct rockchip_cpuclk_reg_data *reg_data,
    250			const struct rockchip_cpuclk_rate_table *rates,
    251			int nrates, void __iomem *reg_base, spinlock_t *lock)
    252{
    253	struct rockchip_cpuclk *cpuclk;
    254	struct clk_init_data init;
    255	struct clk *clk, *cclk;
    256	int ret;
    257
    258	if (num_parents < 2) {
    259		pr_err("%s: needs at least two parent clocks\n", __func__);
    260		return ERR_PTR(-EINVAL);
    261	}
    262
    263	cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
    264	if (!cpuclk)
    265		return ERR_PTR(-ENOMEM);
    266
    267	init.name = name;
    268	init.parent_names = &parent_names[reg_data->mux_core_main];
    269	init.num_parents = 1;
    270	init.ops = &rockchip_cpuclk_ops;
    271
    272	/* only allow rate changes when we have a rate table */
    273	init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0;
    274
    275	/* disallow automatic parent changes by ccf */
    276	init.flags |= CLK_SET_RATE_NO_REPARENT;
    277
    278	init.flags |= CLK_GET_RATE_NOCACHE;
    279
    280	cpuclk->reg_base = reg_base;
    281	cpuclk->lock = lock;
    282	cpuclk->reg_data = reg_data;
    283	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
    284	cpuclk->hw.init = &init;
    285
    286	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
    287	if (!cpuclk->alt_parent) {
    288		pr_err("%s: could not lookup alternate parent: (%d)\n",
    289		       __func__, reg_data->mux_core_alt);
    290		ret = -EINVAL;
    291		goto free_cpuclk;
    292	}
    293
    294	ret = clk_prepare_enable(cpuclk->alt_parent);
    295	if (ret) {
    296		pr_err("%s: could not enable alternate parent\n",
    297		       __func__);
    298		goto free_cpuclk;
    299	}
    300
    301	clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
    302	if (!clk) {
    303		pr_err("%s: could not lookup parent clock: (%d) %s\n",
    304		       __func__, reg_data->mux_core_main,
    305		       parent_names[reg_data->mux_core_main]);
    306		ret = -EINVAL;
    307		goto free_alt_parent;
    308	}
    309
    310	ret = clk_notifier_register(clk, &cpuclk->clk_nb);
    311	if (ret) {
    312		pr_err("%s: failed to register clock notifier for %s\n",
    313				__func__, name);
    314		goto free_alt_parent;
    315	}
    316
    317	if (nrates > 0) {
    318		cpuclk->rate_count = nrates;
    319		cpuclk->rate_table = kmemdup(rates,
    320					     sizeof(*rates) * nrates,
    321					     GFP_KERNEL);
    322		if (!cpuclk->rate_table) {
    323			ret = -ENOMEM;
    324			goto unregister_notifier;
    325		}
    326	}
    327
    328	cclk = clk_register(NULL, &cpuclk->hw);
    329	if (IS_ERR(cclk)) {
    330		pr_err("%s: could not register cpuclk %s\n", __func__,	name);
    331		ret = PTR_ERR(cclk);
    332		goto free_rate_table;
    333	}
    334
    335	return cclk;
    336
    337free_rate_table:
    338	kfree(cpuclk->rate_table);
    339unregister_notifier:
    340	clk_notifier_unregister(clk, &cpuclk->clk_nb);
    341free_alt_parent:
    342	clk_disable_unprepare(cpuclk->alt_parent);
    343free_cpuclk:
    344	kfree(cpuclk);
    345	return ERR_PTR(ret);
    346}