cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-cpu.h (2249B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
      4 *
      5 * Common Clock Framework support for all PLL's in Samsung platforms
      6*/
      7
      8#ifndef __SAMSUNG_CLK_CPU_H
      9#define __SAMSUNG_CLK_CPU_H
     10
     11#include "clk.h"
     12
     13/**
     14 * struct exynos_cpuclk_data: config data to setup cpu clocks.
     15 * @prate: frequency of the primary parent clock (in KHz).
     16 * @div0: value to be programmed in the div_cpu0 register.
     17 * @div1: value to be programmed in the div_cpu1 register.
     18 *
     19 * This structure holds the divider configuration data for dividers in the CPU
     20 * clock domain. The parent frequency at which these divider values are valid is
     21 * specified in @prate. The @prate is the frequency of the primary parent clock.
     22 * For CPU clock domains that do not have a DIV1 register, the @div1 member
     23 * value is not used.
     24 */
     25struct exynos_cpuclk_cfg_data {
     26	unsigned long	prate;
     27	unsigned long	div0;
     28	unsigned long	div1;
     29};
     30
     31/**
     32 * struct exynos_cpuclk: information about clock supplied to a CPU core.
     33 * @hw:	handle between CCF and CPU clock.
     34 * @alt_parent: alternate parent clock to use when switching the speed
     35 *	of the primary parent clock.
     36 * @ctrl_base:	base address of the clock controller.
     37 * @lock: cpu clock domain register access lock.
     38 * @cfg: cpu clock rate configuration data.
     39 * @num_cfgs: number of array elements in @cfg array.
     40 * @clk_nb: clock notifier registered for changes in clock speed of the
     41 *	primary parent clock.
     42 * @flags: configuration flags for the CPU clock.
     43 *
     44 * This structure holds information required for programming the CPU clock for
     45 * various clock speeds.
     46 */
     47struct exynos_cpuclk {
     48	struct clk_hw				hw;
     49	const struct clk_hw			*alt_parent;
     50	void __iomem				*ctrl_base;
     51	spinlock_t				*lock;
     52	const struct exynos_cpuclk_cfg_data	*cfg;
     53	const unsigned long			num_cfgs;
     54	struct notifier_block			clk_nb;
     55	unsigned long				flags;
     56
     57/* The CPU clock registers have DIV1 configuration register */
     58#define CLK_CPU_HAS_DIV1		(1 << 0)
     59/* When ALT parent is active, debug clocks need safe divider values */
     60#define CLK_CPU_NEEDS_DEBUG_ALT_DIV	(1 << 1)
     61/* The CPU clock registers have Exynos5433-compatible layout */
     62#define CLK_CPU_HAS_E5433_REGS_LAYOUT	(1 << 2)
     63};
     64
     65#endif /* __SAMSUNG_CLK_CPU_H */