cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-pll.h (2865B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
      4 * Copyright (c) 2013 Linaro Ltd.
      5 *
      6 * Common Clock Framework support for all PLL's in Samsung platforms
      7*/
      8
      9#ifndef __SAMSUNG_CLK_PLL_H
     10#define __SAMSUNG_CLK_PLL_H
     11
     12enum samsung_pll_type {
     13	pll_2126,
     14	pll_3000,
     15	pll_35xx,
     16	pll_36xx,
     17	pll_2550,
     18	pll_2650,
     19	pll_4500,
     20	pll_4502,
     21	pll_4508,
     22	pll_4600,
     23	pll_4650,
     24	pll_4650c,
     25	pll_6552,
     26	pll_6552_s3c2416,
     27	pll_6553,
     28	pll_s3c2410_mpll,
     29	pll_s3c2410_upll,
     30	pll_s3c2440_mpll,
     31	pll_2550x,
     32	pll_2550xx,
     33	pll_2650x,
     34	pll_2650xx,
     35	pll_1417x,
     36	pll_1450x,
     37	pll_1451x,
     38	pll_1452x,
     39	pll_1460x,
     40	pll_0822x,
     41	pll_0831x,
     42	pll_142xx,
     43};
     44
     45#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
     46	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
     47#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
     48	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
     49
     50#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\
     51	{							\
     52		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
     53				_m, _p, _s, 0, 16),		\
     54		.mdiv	=	(_m),				\
     55		.pdiv	=	(_p),				\
     56		.sdiv	=	(_s),				\
     57	}
     58
     59#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s)		\
     60	{							\
     61		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
     62				_m + 8, _p + 2, _s, 0, 16),	\
     63		.mdiv	=	(_m),				\
     64		.pdiv	=	(_p),				\
     65		.sdiv	=	(_s),				\
     66	}
     67
     68#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s)		\
     69	{							\
     70		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
     71				2 * (_m + 8), _p + 2, _s, 0, 16), \
     72		.mdiv	=	(_m),				\
     73		.pdiv	=	(_p),				\
     74		.sdiv	=	(_s),				\
     75	}
     76
     77#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\
     78	{							\
     79		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
     80				_m, _p, _s, _k, 16),		\
     81		.mdiv	=	(_m),				\
     82		.pdiv	=	(_p),				\
     83		.sdiv	=	(_s),				\
     84		.kdiv	=	(_k),				\
     85	}
     86
     87#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\
     88	{							\
     89		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
     90				_m, _p, _s - 1, 0, 16),		\
     91		.mdiv	=	(_m),				\
     92		.pdiv	=	(_p),				\
     93		.sdiv	=	(_s),				\
     94		.afc	=	(_afc),				\
     95	}
     96
     97#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\
     98	{							\
     99		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
    100				_m, _p, _s, _k, 16),		\
    101		.mdiv	=	(_m),				\
    102		.pdiv	=	(_p),				\
    103		.sdiv	=	(_s),				\
    104		.kdiv	=	(_k),				\
    105		.vsel	=	(_vsel),			\
    106	}
    107
    108#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
    109	{							\
    110		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
    111				_m, _p, _s, _k, 10),		\
    112		.mdiv	=	(_m),				\
    113		.pdiv	=	(_p),				\
    114		.sdiv	=	(_s),				\
    115		.kdiv	=	(_k),				\
    116		.mfr	=	(_mfr),				\
    117		.mrr	=	(_mrr),				\
    118		.vsel	=	(_vsel),			\
    119	}
    120
    121/* NOTE: Rate table should be kept sorted in descending order. */
    122
    123struct samsung_pll_rate_table {
    124	unsigned int rate;
    125	unsigned int pdiv;
    126	unsigned int mdiv;
    127	unsigned int sdiv;
    128	unsigned int kdiv;
    129	unsigned int afc;
    130	unsigned int mfr;
    131	unsigned int mrr;
    132	unsigned int vsel;
    133};
    134
    135#endif /* __SAMSUNG_CLK_PLL_H */