cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-pll-a10.c (3110B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2015 Altera Corporation. All rights reserved
      4 */
      5#include <linux/slab.h>
      6#include <linux/clk-provider.h>
      7#include <linux/io.h>
      8#include <linux/of.h>
      9#include <linux/of_address.h>
     10
     11#include "clk.h"
     12
     13/* Clock Manager offsets */
     14#define CLK_MGR_PLL_CLK_SRC_SHIFT	8
     15#define CLK_MGR_PLL_CLK_SRC_MASK	0x3
     16
     17/* Clock bypass bits */
     18#define SOCFPGA_PLL_BG_PWRDWN		0
     19#define SOCFPGA_PLL_PWR_DOWN		1
     20#define SOCFPGA_PLL_EXT_ENA		2
     21#define SOCFPGA_PLL_DIVF_MASK		0x00001FFF
     22#define SOCFPGA_PLL_DIVF_SHIFT	0
     23#define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
     24#define SOCFPGA_PLL_DIVQ_SHIFT	16
     25#define SOCFGPA_MAX_PARENTS	5
     26
     27#define SOCFPGA_MAIN_PLL_CLK		"main_pll"
     28#define SOCFPGA_PERIP_PLL_CLK		"periph_pll"
     29
     30#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
     31
     32void __iomem *clk_mgr_a10_base_addr;
     33
     34static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
     35					 unsigned long parent_rate)
     36{
     37	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
     38	unsigned long divf, divq, reg;
     39	unsigned long long vco_freq;
     40
     41	/* read VCO1 reg for numerator and denominator */
     42	reg = readl(socfpgaclk->hw.reg + 0x4);
     43	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
     44	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
     45	vco_freq = (unsigned long long)parent_rate * (divf + 1);
     46	do_div(vco_freq, (1 + divq));
     47	return (unsigned long)vco_freq;
     48}
     49
     50static u8 clk_pll_get_parent(struct clk_hw *hwclk)
     51{
     52	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
     53	u32 pll_src;
     54
     55	pll_src = readl(socfpgaclk->hw.reg);
     56
     57	return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
     58		CLK_MGR_PLL_CLK_SRC_MASK;
     59}
     60
     61static const struct clk_ops clk_pll_ops = {
     62	.recalc_rate = clk_pll_recalc_rate,
     63	.get_parent = clk_pll_get_parent,
     64};
     65
     66static struct clk_hw * __init __socfpga_pll_init(struct device_node *node,
     67	const struct clk_ops *ops)
     68{
     69	u32 reg;
     70	struct clk_hw *hw_clk;
     71	struct socfpga_pll *pll_clk;
     72	const char *clk_name = node->name;
     73	const char *parent_name[SOCFGPA_MAX_PARENTS];
     74	struct clk_init_data init;
     75	struct device_node *clkmgr_np;
     76	int i = 0;
     77
     78	of_property_read_u32(node, "reg", &reg);
     79
     80	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
     81	if (WARN_ON(!pll_clk))
     82		return NULL;
     83
     84	clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
     85	clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0);
     86	of_node_put(clkmgr_np);
     87	BUG_ON(!clk_mgr_a10_base_addr);
     88	pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;
     89
     90	of_property_read_string(node, "clock-output-names", &clk_name);
     91
     92	init.name = clk_name;
     93	init.ops = ops;
     94	init.flags = 0;
     95
     96	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
     97			of_clk_get_parent_name(node, i)) != NULL)
     98		i++;
     99	init.num_parents = i;
    100	init.parent_names = parent_name;
    101	pll_clk->hw.hw.init = &init;
    102
    103	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
    104	hw_clk = &pll_clk->hw.hw;
    105
    106	if (clk_hw_register(NULL, hw_clk)) {
    107		kfree(pll_clk);
    108		return NULL;
    109	}
    110	of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
    111	return hw_clk;
    112}
    113
    114void __init socfpga_a10_pll_init(struct device_node *node)
    115{
    116	__socfpga_pll_init(node, &clk_pll_ops);
    117}