cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clk-starfive-jh7100-audio.c (6382B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * StarFive JH7100 Audio Clock Driver
      4 *
      5 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
      6 */
      7
      8#include <linux/bits.h>
      9#include <linux/clk-provider.h>
     10#include <linux/device.h>
     11#include <linux/kernel.h>
     12#include <linux/mod_devicetable.h>
     13#include <linux/module.h>
     14#include <linux/of_device.h>
     15#include <linux/platform_device.h>
     16
     17#include <dt-bindings/clock/starfive-jh7100-audio.h>
     18
     19#include "clk-starfive-jh7100.h"
     20
     21/* external clocks */
     22#define JH7100_AUDCLK_AUDIO_SRC			(JH7100_AUDCLK_END + 0)
     23#define JH7100_AUDCLK_AUDIO_12288		(JH7100_AUDCLK_END + 1)
     24#define JH7100_AUDCLK_DOM7AHB_BUS		(JH7100_AUDCLK_END + 2)
     25#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD		(JH7100_AUDCLK_END + 3)
     26#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD	(JH7100_AUDCLK_END + 4)
     27#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD		(JH7100_AUDCLK_END + 5)
     28#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD	(JH7100_AUDCLK_END + 6)
     29#define JH7100_AUDCLK_VAD_INTMEM                (JH7100_AUDCLK_END + 7)
     30
     31static const struct jh7100_clk_data jh7100_audclk_data[] = {
     32	JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
     33		    JH7100_AUDCLK_AUDIO_SRC,
     34		    JH7100_AUDCLK_AUDIO_12288),
     35	JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
     36		    JH7100_AUDCLK_AUDIO_SRC,
     37		    JH7100_AUDCLK_AUDIO_12288),
     38	JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
     39	JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
     40		    JH7100_AUDCLK_ADC_MCLK,
     41		    JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
     42	JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
     43	JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
     44		    JH7100_AUDCLK_I2SADC_BCLK_N,
     45		    JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
     46		    JH7100_AUDCLK_I2SADC_BCLK),
     47	JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
     48	JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
     49		    JH7100_AUDCLK_AUDIO_SRC,
     50		    JH7100_AUDCLK_AUDIO_12288),
     51	JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
     52	JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
     53		    JH7100_AUDCLK_AUDIO_SRC,
     54		    JH7100_AUDCLK_AUDIO_12288),
     55	JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
     56	JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
     57	JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
     58		    JH7100_AUDCLK_AUDIO_SRC,
     59		    JH7100_AUDCLK_AUDIO_12288),
     60	JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
     61	JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
     62		    JH7100_AUDCLK_DAC_MCLK,
     63		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
     64	JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
     65	JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
     66		    JH7100_AUDCLK_I2S1_MCLK,
     67		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
     68	JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
     69	JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
     70		    JH7100_AUDCLK_I2S1_MCLK,
     71		    JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
     72	JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
     73	JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
     74		    JH7100_AUDCLK_I2S1_BCLK_N,
     75		    JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
     76	JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
     77	JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
     78	JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
     79	JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
     80	JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
     81	JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
     82	JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
     83	JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
     84		    JH7100_AUDCLK_VAD_INTMEM,
     85		    JH7100_AUDCLK_AUDIO_12288),
     86};
     87
     88static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
     89{
     90	struct jh7100_clk_priv *priv = data;
     91	unsigned int idx = clkspec->args[0];
     92
     93	if (idx < JH7100_AUDCLK_END)
     94		return &priv->reg[idx].hw;
     95
     96	return ERR_PTR(-EINVAL);
     97}
     98
     99static int jh7100_audclk_probe(struct platform_device *pdev)
    100{
    101	struct jh7100_clk_priv *priv;
    102	unsigned int idx;
    103	int ret;
    104
    105	priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL);
    106	if (!priv)
    107		return -ENOMEM;
    108
    109	spin_lock_init(&priv->rmw_lock);
    110	priv->dev = &pdev->dev;
    111	priv->base = devm_platform_ioremap_resource(pdev, 0);
    112	if (IS_ERR(priv->base))
    113		return PTR_ERR(priv->base);
    114
    115	for (idx = 0; idx < JH7100_AUDCLK_END; idx++) {
    116		u32 max = jh7100_audclk_data[idx].max;
    117		struct clk_parent_data parents[4] = {};
    118		struct clk_init_data init = {
    119			.name = jh7100_audclk_data[idx].name,
    120			.ops = starfive_jh7100_clk_ops(max),
    121			.parent_data = parents,
    122			.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
    123			.flags = jh7100_audclk_data[idx].flags,
    124		};
    125		struct jh7100_clk *clk = &priv->reg[idx];
    126		unsigned int i;
    127
    128		for (i = 0; i < init.num_parents; i++) {
    129			unsigned int pidx = jh7100_audclk_data[idx].parents[i];
    130
    131			if (pidx < JH7100_AUDCLK_END)
    132				parents[i].hw = &priv->reg[pidx].hw;
    133			else if (pidx == JH7100_AUDCLK_AUDIO_SRC)
    134				parents[i].fw_name = "audio_src";
    135			else if (pidx == JH7100_AUDCLK_AUDIO_12288)
    136				parents[i].fw_name = "audio_12288";
    137			else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS)
    138				parents[i].fw_name = "dom7ahb_bus";
    139		}
    140
    141		clk->hw.init = &init;
    142		clk->idx = idx;
    143		clk->max_div = max & JH7100_CLK_DIV_MASK;
    144
    145		ret = devm_clk_hw_register(priv->dev, &clk->hw);
    146		if (ret)
    147			return ret;
    148	}
    149
    150	return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv);
    151}
    152
    153static const struct of_device_id jh7100_audclk_match[] = {
    154	{ .compatible = "starfive,jh7100-audclk" },
    155	{ /* sentinel */ }
    156};
    157MODULE_DEVICE_TABLE(of, jh7100_audclk_match);
    158
    159static struct platform_driver jh7100_audclk_driver = {
    160	.probe = jh7100_audclk_probe,
    161	.driver = {
    162		.name = "clk-starfive-jh7100-audio",
    163		.of_match_table = jh7100_audclk_match,
    164	},
    165};
    166module_platform_driver(jh7100_audclk_driver);
    167
    168MODULE_AUTHOR("Emil Renner Berthing");
    169MODULE_DESCRIPTION("StarFive JH7100 audio clock driver");
    170MODULE_LICENSE("GPL v2");