cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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reset-stm32.c (3037B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
      4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
      5 */
      6
      7#include <linux/of.h>
      8#include <linux/platform_device.h>
      9#include <linux/regmap.h>
     10#include <linux/reset-controller.h>
     11#include <linux/slab.h>
     12#include <linux/spinlock.h>
     13
     14#include "clk-stm32-core.h"
     15
     16#define STM32_RESET_ID_MASK GENMASK(15, 0)
     17
     18struct stm32_reset_data {
     19	/* reset lock */
     20	spinlock_t			lock;
     21	struct reset_controller_dev	rcdev;
     22	void __iomem			*membase;
     23	u32				clear_offset;
     24};
     25
     26static inline struct stm32_reset_data *
     27to_stm32_reset_data(struct reset_controller_dev *rcdev)
     28{
     29	return container_of(rcdev, struct stm32_reset_data, rcdev);
     30}
     31
     32static int stm32_reset_update(struct reset_controller_dev *rcdev,
     33			      unsigned long id, bool assert)
     34{
     35	struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
     36	int reg_width = sizeof(u32);
     37	int bank = id / (reg_width * BITS_PER_BYTE);
     38	int offset = id % (reg_width * BITS_PER_BYTE);
     39
     40	if (data->clear_offset) {
     41		void __iomem *addr;
     42
     43		addr = data->membase + (bank * reg_width);
     44		if (!assert)
     45			addr += data->clear_offset;
     46
     47		writel(BIT(offset), addr);
     48
     49	} else {
     50		unsigned long flags;
     51		u32 reg;
     52
     53		spin_lock_irqsave(&data->lock, flags);
     54
     55		reg = readl(data->membase + (bank * reg_width));
     56
     57		if (assert)
     58			reg |= BIT(offset);
     59		else
     60			reg &= ~BIT(offset);
     61
     62		writel(reg, data->membase + (bank * reg_width));
     63
     64		spin_unlock_irqrestore(&data->lock, flags);
     65	}
     66
     67	return 0;
     68}
     69
     70static int stm32_reset_assert(struct reset_controller_dev *rcdev,
     71			      unsigned long id)
     72{
     73	return stm32_reset_update(rcdev, id, true);
     74}
     75
     76static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
     77				unsigned long id)
     78{
     79	return stm32_reset_update(rcdev, id, false);
     80}
     81
     82static int stm32_reset_status(struct reset_controller_dev *rcdev,
     83			      unsigned long id)
     84{
     85	struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
     86	int reg_width = sizeof(u32);
     87	int bank = id / (reg_width * BITS_PER_BYTE);
     88	int offset = id % (reg_width * BITS_PER_BYTE);
     89	u32 reg;
     90
     91	reg = readl(data->membase + (bank * reg_width));
     92
     93	return !!(reg & BIT(offset));
     94}
     95
     96static const struct reset_control_ops stm32_reset_ops = {
     97	.assert		= stm32_reset_assert,
     98	.deassert	= stm32_reset_deassert,
     99	.status		= stm32_reset_status,
    100};
    101
    102int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,
    103			 void __iomem *base)
    104{
    105	const struct stm32_rcc_match_data *data = match->data;
    106	struct stm32_reset_data *reset_data = NULL;
    107
    108	data = match->data;
    109
    110	reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
    111	if (!reset_data)
    112		return -ENOMEM;
    113
    114	spin_lock_init(&reset_data->lock);
    115	reset_data->membase = base;
    116	reset_data->rcdev.owner = THIS_MODULE;
    117	reset_data->rcdev.ops = &stm32_reset_ops;
    118	reset_data->rcdev.of_node = dev_of_node(dev);
    119	reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
    120	reset_data->clear_offset = data->clear_offset;
    121
    122	return reset_controller_register(&reset_data->rcdev);
    123}