ccu-sun50i-a100.h (1267B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 */ 5 6#ifndef _CCU_SUN50I_A100_H_ 7#define _CCU_SUN50I_A100_H_ 8 9#include <dt-bindings/clock/sun50i-a100-ccu.h> 10#include <dt-bindings/reset/sun50i-a100-ccu.h> 11 12#define CLK_OSC12M 0 13#define CLK_PLL_CPUX 1 14#define CLK_PLL_DDR0 2 15 16/* PLL_PERIPH0 exported for PRCM */ 17 18#define CLK_PLL_PERIPH0_2X 4 19#define CLK_PLL_PERIPH1 5 20#define CLK_PLL_PERIPH1_2X 6 21#define CLK_PLL_GPU 7 22#define CLK_PLL_VIDEO0 8 23#define CLK_PLL_VIDEO0_2X 9 24#define CLK_PLL_VIDEO0_4X 10 25#define CLK_PLL_VIDEO1 11 26#define CLK_PLL_VIDEO1_2X 12 27#define CLK_PLL_VIDEO1_4X 13 28#define CLK_PLL_VIDEO2 14 29#define CLK_PLL_VIDEO2_2X 15 30#define CLK_PLL_VIDEO2_4X 16 31#define CLK_PLL_VIDEO3 17 32#define CLK_PLL_VIDEO3_2X 18 33#define CLK_PLL_VIDEO3_4X 19 34#define CLK_PLL_VE 20 35#define CLK_PLL_COM 21 36#define CLK_PLL_COM_AUDIO 22 37#define CLK_PLL_AUDIO 23 38 39/* CPUX clock exported for DVFS */ 40 41#define CLK_AXI 25 42#define CLK_CPUX_APB 26 43#define CLK_PSI_AHB1_AHB2 27 44#define CLK_AHB3 28 45 46/* APB1 clock exported for PIO */ 47 48#define CLK_APB2 30 49 50/* All module clocks and bus gates are exported except DRAM */ 51 52#define CLK_BUS_DRAM 58 53 54#define CLK_NUMBER (CLK_CSI_ISP + 1) 55 56#endif /* _CCU_SUN50I_A100_H_ */