cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ccu-sun8i-h3.c (38907B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
      4 */
      5
      6#include <linux/clk-provider.h>
      7#include <linux/io.h>
      8#include <linux/module.h>
      9#include <linux/of_device.h>
     10#include <linux/platform_device.h>
     11
     12#include "ccu_common.h"
     13#include "ccu_reset.h"
     14
     15#include "ccu_div.h"
     16#include "ccu_gate.h"
     17#include "ccu_mp.h"
     18#include "ccu_mult.h"
     19#include "ccu_nk.h"
     20#include "ccu_nkm.h"
     21#include "ccu_nkmp.h"
     22#include "ccu_nm.h"
     23#include "ccu_phase.h"
     24#include "ccu_sdm.h"
     25
     26#include "ccu-sun8i-h3.h"
     27
     28static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
     29				     "osc24M", 0x000,
     30				     8, 5,	/* N */
     31				     4, 2,	/* K */
     32				     0, 2,	/* M */
     33				     16, 2,	/* P */
     34				     BIT(31),	/* gate */
     35				     BIT(28),	/* lock */
     36				     CLK_SET_RATE_UNGATE);
     37
     38/*
     39 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
     40 * the base (2x, 4x and 8x), and one variable divider (the one true
     41 * pll audio).
     42 *
     43 * With sigma-delta modulation for fractional-N on the audio PLL,
     44 * we have to use specific dividers. This means the variable divider
     45 * can no longer be used, as the audio codec requests the exact clock
     46 * rates we support through this mechanism. So we now hard code the
     47 * variable divider to 1. This means the clock rates will no longer
     48 * match the clock names.
     49 */
     50#define SUN8I_H3_PLL_AUDIO_REG	0x008
     51
     52static struct ccu_sdm_setting pll_audio_sdm_table[] = {
     53	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
     54	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
     55};
     56
     57static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
     58				       "osc24M", 0x008,
     59				       8, 7,	/* N */
     60				       0, 5,	/* M */
     61				       pll_audio_sdm_table, BIT(24),
     62				       0x284, BIT(31),
     63				       BIT(31),	/* gate */
     64				       BIT(28),	/* lock */
     65				       CLK_SET_RATE_UNGATE);
     66
     67static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
     68						"osc24M", 0x0010,
     69						192000000, /* Minimum rate */
     70						912000000, /* Maximum rate */
     71						8, 7,      /* N */
     72						0, 4,	   /* M */
     73						BIT(24),   /* frac enable */
     74						BIT(25),   /* frac select */
     75						270000000, /* frac rate 0 */
     76						297000000, /* frac rate 1 */
     77						BIT(31),   /* gate */
     78						BIT(28),   /* lock */
     79						CLK_SET_RATE_UNGATE);
     80
     81static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
     82					"osc24M", 0x0018,
     83					8, 7,		/* N */
     84					0, 4,		/* M */
     85					BIT(24),	/* frac enable */
     86					BIT(25),	/* frac select */
     87					270000000,	/* frac rate 0 */
     88					297000000,	/* frac rate 1 */
     89					BIT(31),	/* gate */
     90					BIT(28),	/* lock */
     91					CLK_SET_RATE_UNGATE);
     92
     93static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
     94				    "osc24M", 0x020,
     95				    8, 5,	/* N */
     96				    4, 2,	/* K */
     97				    0, 2,	/* M */
     98				    BIT(31),	/* gate */
     99				    BIT(28),	/* lock */
    100				    CLK_SET_RATE_UNGATE);
    101
    102static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
    103					   "osc24M", 0x028,
    104					   8, 5,	/* N */
    105					   4, 2,	/* K */
    106					   BIT(31),	/* gate */
    107					   BIT(28),	/* lock */
    108					   2,		/* post-div */
    109					   CLK_SET_RATE_UNGATE);
    110
    111static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
    112					"osc24M", 0x0038,
    113					8, 7,		/* N */
    114					0, 4,		/* M */
    115					BIT(24),	/* frac enable */
    116					BIT(25),	/* frac select */
    117					270000000,	/* frac rate 0 */
    118					297000000,	/* frac rate 1 */
    119					BIT(31),	/* gate */
    120					BIT(28),	/* lock */
    121					CLK_SET_RATE_UNGATE);
    122
    123static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
    124					   "osc24M", 0x044,
    125					   8, 5,	/* N */
    126					   4, 2,	/* K */
    127					   BIT(31),	/* gate */
    128					   BIT(28),	/* lock */
    129					   2,		/* post-div */
    130					   CLK_SET_RATE_UNGATE);
    131
    132static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
    133					"osc24M", 0x0048,
    134					8, 7,		/* N */
    135					0, 4,		/* M */
    136					BIT(24),	/* frac enable */
    137					BIT(25),	/* frac select */
    138					270000000,	/* frac rate 0 */
    139					297000000,	/* frac rate 1 */
    140					BIT(31),	/* gate */
    141					BIT(28),	/* lock */
    142					CLK_SET_RATE_UNGATE);
    143
    144static const char * const cpux_parents[] = { "osc32k", "osc24M",
    145					     "pll-cpux" , "pll-cpux" };
    146static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
    147		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
    148
    149static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
    150
    151static const char * const ahb1_parents[] = { "osc32k", "osc24M",
    152					     "axi" , "pll-periph0" };
    153static const struct ccu_mux_var_prediv ahb1_predivs[] = {
    154	{ .index = 3, .shift = 6, .width = 2 },
    155};
    156static struct ccu_div ahb1_clk = {
    157	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
    158
    159	.mux		= {
    160		.shift	= 12,
    161		.width	= 2,
    162
    163		.var_predivs	= ahb1_predivs,
    164		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
    165	},
    166
    167	.common		= {
    168		.reg		= 0x054,
    169		.features	= CCU_FEATURE_VARIABLE_PREDIV,
    170		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
    171						      ahb1_parents,
    172						      &ccu_div_ops,
    173						      0),
    174	},
    175};
    176
    177static struct clk_div_table apb1_div_table[] = {
    178	{ .val = 0, .div = 2 },
    179	{ .val = 1, .div = 2 },
    180	{ .val = 2, .div = 4 },
    181	{ .val = 3, .div = 8 },
    182	{ /* Sentinel */ },
    183};
    184static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
    185			   0x054, 8, 2, apb1_div_table, 0);
    186
    187static const char * const apb2_parents[] = { "osc32k", "osc24M",
    188					     "pll-periph0" , "pll-periph0" };
    189static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
    190			     0, 5,	/* M */
    191			     16, 2,	/* P */
    192			     24, 2,	/* mux */
    193			     0);
    194
    195static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
    196static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
    197	{ .index = 1, .div = 2 },
    198};
    199static struct ccu_mux ahb2_clk = {
    200	.mux		= {
    201		.shift	= 0,
    202		.width	= 1,
    203		.fixed_predivs	= ahb2_fixed_predivs,
    204		.n_predivs	= ARRAY_SIZE(ahb2_fixed_predivs),
    205	},
    206
    207	.common		= {
    208		.reg		= 0x05c,
    209		.features	= CCU_FEATURE_FIXED_PREDIV,
    210		.hw.init	= CLK_HW_INIT_PARENTS("ahb2",
    211						      ahb2_parents,
    212						      &ccu_mux_ops,
    213						      0),
    214	},
    215};
    216
    217static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
    218		      0x060, BIT(5), 0);
    219static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
    220		      0x060, BIT(6), 0);
    221static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
    222		      0x060, BIT(8), 0);
    223static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
    224		      0x060, BIT(9), 0);
    225static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
    226		      0x060, BIT(10), 0);
    227static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
    228		      0x060, BIT(13), 0);
    229static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
    230		      0x060, BIT(14), 0);
    231static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb2",
    232		      0x060, BIT(17), 0);
    233static SUNXI_CCU_GATE(bus_ts_clk,	"bus-ts",	"ahb1",
    234		      0x060, BIT(18), 0);
    235static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
    236		      0x060, BIT(19), 0);
    237static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
    238		      0x060, BIT(20), 0);
    239static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
    240		      0x060, BIT(21), 0);
    241static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
    242		      0x060, BIT(23), 0);
    243static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
    244		      0x060, BIT(24), 0);
    245static SUNXI_CCU_GATE(bus_ehci1_clk,	"bus-ehci1",	"ahb2",
    246		      0x060, BIT(25), 0);
    247static SUNXI_CCU_GATE(bus_ehci2_clk,	"bus-ehci2",	"ahb2",
    248		      0x060, BIT(26), 0);
    249static SUNXI_CCU_GATE(bus_ehci3_clk,	"bus-ehci3",	"ahb2",
    250		      0x060, BIT(27), 0);
    251static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
    252		      0x060, BIT(28), 0);
    253static SUNXI_CCU_GATE(bus_ohci1_clk,	"bus-ohci1",	"ahb2",
    254		      0x060, BIT(29), 0);
    255static SUNXI_CCU_GATE(bus_ohci2_clk,	"bus-ohci2",	"ahb2",
    256		      0x060, BIT(30), 0);
    257static SUNXI_CCU_GATE(bus_ohci3_clk,	"bus-ohci3",	"ahb2",
    258		      0x060, BIT(31), 0);
    259
    260static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
    261		      0x064, BIT(0), 0);
    262static SUNXI_CCU_GATE(bus_tcon0_clk,	"bus-tcon0",	"ahb1",
    263		      0x064, BIT(3), 0);
    264static SUNXI_CCU_GATE(bus_tcon1_clk,	"bus-tcon1",	"ahb1",
    265		      0x064, BIT(4), 0);
    266static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb1",
    267		      0x064, BIT(5), 0);
    268static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb1",
    269		      0x064, BIT(8), 0);
    270static SUNXI_CCU_GATE(bus_tve_clk,	"bus-tve",	"ahb1",
    271		      0x064, BIT(9), 0);
    272static SUNXI_CCU_GATE(bus_hdmi_clk,	"bus-hdmi",	"ahb1",
    273		      0x064, BIT(11), 0);
    274static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
    275		      0x064, BIT(12), 0);
    276static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
    277		      0x064, BIT(20), 0);
    278static SUNXI_CCU_GATE(bus_msgbox_clk,	"bus-msgbox",	"ahb1",
    279		      0x064, BIT(21), 0);
    280static SUNXI_CCU_GATE(bus_spinlock_clk,	"bus-spinlock",	"ahb1",
    281		      0x064, BIT(22), 0);
    282
    283static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
    284		      0x068, BIT(0), 0);
    285static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb1",
    286		      0x068, BIT(1), 0);
    287static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
    288		      0x068, BIT(5), 0);
    289static SUNXI_CCU_GATE(bus_ths_clk,	"bus-ths",	"apb1",
    290		      0x068, BIT(8), 0);
    291static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
    292		      0x068, BIT(12), 0);
    293static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
    294		      0x068, BIT(13), 0);
    295static SUNXI_CCU_GATE(bus_i2s2_clk,	"bus-i2s2",	"apb1",
    296		      0x068, BIT(14), 0);
    297
    298static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
    299		      0x06c, BIT(0), 0);
    300static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
    301		      0x06c, BIT(1), 0);
    302static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
    303		      0x06c, BIT(2), 0);
    304static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
    305		      0x06c, BIT(16), 0);
    306static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
    307		      0x06c, BIT(17), 0);
    308static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
    309		      0x06c, BIT(18), 0);
    310static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
    311		      0x06c, BIT(19), 0);
    312static SUNXI_CCU_GATE(bus_scr0_clk,	"bus-scr0",	"apb2",
    313		      0x06c, BIT(20), 0);
    314static SUNXI_CCU_GATE(bus_scr1_clk,	"bus-scr1",	"apb2",
    315		      0x06c, BIT(21), 0);
    316
    317static SUNXI_CCU_GATE(bus_ephy_clk,	"bus-ephy",	"ahb1",
    318		      0x070, BIT(0), 0);
    319static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
    320		      0x070, BIT(7), 0);
    321
    322static struct clk_div_table ths_div_table[] = {
    323	{ .val = 0, .div = 1 },
    324	{ .val = 1, .div = 2 },
    325	{ .val = 2, .div = 4 },
    326	{ .val = 3, .div = 6 },
    327	{ /* Sentinel */ },
    328};
    329static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
    330				     0x074, 0, 2, ths_div_table, BIT(31), 0);
    331
    332static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
    333						     "pll-periph1" };
    334static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
    335				  0, 4,		/* M */
    336				  16, 2,	/* P */
    337				  24, 2,	/* mux */
    338				  BIT(31),	/* gate */
    339				  0);
    340
    341static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
    342				  0, 4,		/* M */
    343				  16, 2,	/* P */
    344				  24, 2,	/* mux */
    345				  BIT(31),	/* gate */
    346				  0);
    347
    348static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
    349		       0x088, 20, 3, 0);
    350static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
    351		       0x088, 8, 3, 0);
    352
    353static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
    354				  0, 4,		/* M */
    355				  16, 2,	/* P */
    356				  24, 2,	/* mux */
    357				  BIT(31),	/* gate */
    358				  0);
    359
    360static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
    361		       0x08c, 20, 3, 0);
    362static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
    363		       0x08c, 8, 3, 0);
    364
    365static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
    366				  0, 4,		/* M */
    367				  16, 2,	/* P */
    368				  24, 2,	/* mux */
    369				  BIT(31),	/* gate */
    370				  0);
    371
    372static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
    373		       0x090, 20, 3, 0);
    374static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
    375		       0x090, 8, 3, 0);
    376
    377static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
    378static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
    379				  0, 4,		/* M */
    380				  16, 2,	/* P */
    381				  24, 2,	/* mux */
    382				  BIT(31),	/* gate */
    383				  0);
    384
    385static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
    386				  0, 4,		/* M */
    387				  16, 2,	/* P */
    388				  24, 2,	/* mux */
    389				  BIT(31),	/* gate */
    390				  0);
    391
    392static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
    393				  0, 4,		/* M */
    394				  16, 2,	/* P */
    395				  24, 2,	/* mux */
    396				  BIT(31),	/* gate */
    397				  0);
    398
    399static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
    400				  0, 4,		/* M */
    401				  16, 2,	/* P */
    402				  24, 2,	/* mux */
    403				  BIT(31),	/* gate */
    404				  0);
    405
    406static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
    407					    "pll-audio-2x", "pll-audio" };
    408static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
    409			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
    410
    411static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
    412			       0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
    413
    414static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
    415			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
    416
    417static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
    418			     0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
    419
    420static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
    421		      0x0cc, BIT(8), 0);
    422static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
    423		      0x0cc, BIT(9), 0);
    424static SUNXI_CCU_GATE(usb_phy2_clk,	"usb-phy2",	"osc24M",
    425		      0x0cc, BIT(10), 0);
    426static SUNXI_CCU_GATE(usb_phy3_clk,	"usb-phy3",	"osc24M",
    427		      0x0cc, BIT(11), 0);
    428static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc24M",
    429		      0x0cc, BIT(16), 0);
    430static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"osc24M",
    431		      0x0cc, BIT(17), 0);
    432static SUNXI_CCU_GATE(usb_ohci2_clk,	"usb-ohci2",	"osc24M",
    433		      0x0cc, BIT(18), 0);
    434static SUNXI_CCU_GATE(usb_ohci3_clk,	"usb-ohci3",	"osc24M",
    435		      0x0cc, BIT(19), 0);
    436
    437static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
    438static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
    439			    0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
    440
    441static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
    442		      0x100, BIT(0), 0);
    443static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"dram",
    444		      0x100, BIT(1), 0);
    445static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",	"dram",
    446		      0x100, BIT(2), 0);
    447static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
    448		      0x100, BIT(3), 0);
    449
    450static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
    451static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
    452				 0x104, 0, 4, 24, 3, BIT(31),
    453				 CLK_SET_RATE_PARENT);
    454
    455static const char * const tcon_parents[] = { "pll-video" };
    456static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
    457				 0x118, 0, 4, 24, 3, BIT(31),
    458				 CLK_SET_RATE_PARENT);
    459
    460static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
    461static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
    462				 0x120, 0, 4, 24, 3, BIT(31), 0);
    463
    464static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
    465static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
    466				 0x124, 0, 4, 24, 3, BIT(31), 0);
    467
    468static SUNXI_CCU_GATE(csi_misc_clk,	"csi-misc",	"osc24M",
    469		      0x130, BIT(31), 0);
    470
    471static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
    472static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
    473				 0x134, 16, 4, 24, 3, BIT(31), 0);
    474
    475static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
    476static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
    477				 0x134, 0, 5, 8, 3, BIT(15), 0);
    478
    479static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
    480			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
    481
    482static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
    483		      0x140, BIT(31), CLK_SET_RATE_PARENT);
    484static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
    485		      0x144, BIT(31), 0);
    486
    487static const char * const hdmi_parents[] = { "pll-video" };
    488static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
    489				 0x150, 0, 4, 24, 2, BIT(31),
    490				 CLK_SET_RATE_PARENT);
    491
    492static SUNXI_CCU_GATE(hdmi_ddc_clk,	"hdmi-ddc",	"osc24M",
    493		      0x154, BIT(31), 0);
    494
    495static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
    496static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
    497				 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
    498
    499static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
    500			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
    501
    502static struct ccu_common *sun8i_h3_ccu_clks[] = {
    503	&pll_cpux_clk.common,
    504	&pll_audio_base_clk.common,
    505	&pll_video_clk.common,
    506	&pll_ve_clk.common,
    507	&pll_ddr_clk.common,
    508	&pll_periph0_clk.common,
    509	&pll_gpu_clk.common,
    510	&pll_periph1_clk.common,
    511	&pll_de_clk.common,
    512	&cpux_clk.common,
    513	&axi_clk.common,
    514	&ahb1_clk.common,
    515	&apb1_clk.common,
    516	&apb2_clk.common,
    517	&ahb2_clk.common,
    518	&bus_ce_clk.common,
    519	&bus_dma_clk.common,
    520	&bus_mmc0_clk.common,
    521	&bus_mmc1_clk.common,
    522	&bus_mmc2_clk.common,
    523	&bus_nand_clk.common,
    524	&bus_dram_clk.common,
    525	&bus_emac_clk.common,
    526	&bus_ts_clk.common,
    527	&bus_hstimer_clk.common,
    528	&bus_spi0_clk.common,
    529	&bus_spi1_clk.common,
    530	&bus_otg_clk.common,
    531	&bus_ehci0_clk.common,
    532	&bus_ehci1_clk.common,
    533	&bus_ehci2_clk.common,
    534	&bus_ehci3_clk.common,
    535	&bus_ohci0_clk.common,
    536	&bus_ohci1_clk.common,
    537	&bus_ohci2_clk.common,
    538	&bus_ohci3_clk.common,
    539	&bus_ve_clk.common,
    540	&bus_tcon0_clk.common,
    541	&bus_tcon1_clk.common,
    542	&bus_deinterlace_clk.common,
    543	&bus_csi_clk.common,
    544	&bus_tve_clk.common,
    545	&bus_hdmi_clk.common,
    546	&bus_de_clk.common,
    547	&bus_gpu_clk.common,
    548	&bus_msgbox_clk.common,
    549	&bus_spinlock_clk.common,
    550	&bus_codec_clk.common,
    551	&bus_spdif_clk.common,
    552	&bus_pio_clk.common,
    553	&bus_ths_clk.common,
    554	&bus_i2s0_clk.common,
    555	&bus_i2s1_clk.common,
    556	&bus_i2s2_clk.common,
    557	&bus_i2c0_clk.common,
    558	&bus_i2c1_clk.common,
    559	&bus_i2c2_clk.common,
    560	&bus_uart0_clk.common,
    561	&bus_uart1_clk.common,
    562	&bus_uart2_clk.common,
    563	&bus_uart3_clk.common,
    564	&bus_scr0_clk.common,
    565	&bus_ephy_clk.common,
    566	&bus_dbg_clk.common,
    567	&ths_clk.common,
    568	&nand_clk.common,
    569	&mmc0_clk.common,
    570	&mmc0_sample_clk.common,
    571	&mmc0_output_clk.common,
    572	&mmc1_clk.common,
    573	&mmc1_sample_clk.common,
    574	&mmc1_output_clk.common,
    575	&mmc2_clk.common,
    576	&mmc2_sample_clk.common,
    577	&mmc2_output_clk.common,
    578	&ts_clk.common,
    579	&ce_clk.common,
    580	&spi0_clk.common,
    581	&spi1_clk.common,
    582	&i2s0_clk.common,
    583	&i2s1_clk.common,
    584	&i2s2_clk.common,
    585	&spdif_clk.common,
    586	&usb_phy0_clk.common,
    587	&usb_phy1_clk.common,
    588	&usb_phy2_clk.common,
    589	&usb_phy3_clk.common,
    590	&usb_ohci0_clk.common,
    591	&usb_ohci1_clk.common,
    592	&usb_ohci2_clk.common,
    593	&usb_ohci3_clk.common,
    594	&dram_clk.common,
    595	&dram_ve_clk.common,
    596	&dram_csi_clk.common,
    597	&dram_deinterlace_clk.common,
    598	&dram_ts_clk.common,
    599	&de_clk.common,
    600	&tcon_clk.common,
    601	&tve_clk.common,
    602	&deinterlace_clk.common,
    603	&csi_misc_clk.common,
    604	&csi_sclk_clk.common,
    605	&csi_mclk_clk.common,
    606	&ve_clk.common,
    607	&ac_dig_clk.common,
    608	&avs_clk.common,
    609	&hdmi_clk.common,
    610	&hdmi_ddc_clk.common,
    611	&mbus_clk.common,
    612	&gpu_clk.common,
    613};
    614
    615static struct ccu_common *sun50i_h5_ccu_clks[] = {
    616	&pll_cpux_clk.common,
    617	&pll_audio_base_clk.common,
    618	&pll_video_clk.common,
    619	&pll_ve_clk.common,
    620	&pll_ddr_clk.common,
    621	&pll_periph0_clk.common,
    622	&pll_gpu_clk.common,
    623	&pll_periph1_clk.common,
    624	&pll_de_clk.common,
    625	&cpux_clk.common,
    626	&axi_clk.common,
    627	&ahb1_clk.common,
    628	&apb1_clk.common,
    629	&apb2_clk.common,
    630	&ahb2_clk.common,
    631	&bus_ce_clk.common,
    632	&bus_dma_clk.common,
    633	&bus_mmc0_clk.common,
    634	&bus_mmc1_clk.common,
    635	&bus_mmc2_clk.common,
    636	&bus_nand_clk.common,
    637	&bus_dram_clk.common,
    638	&bus_emac_clk.common,
    639	&bus_ts_clk.common,
    640	&bus_hstimer_clk.common,
    641	&bus_spi0_clk.common,
    642	&bus_spi1_clk.common,
    643	&bus_otg_clk.common,
    644	&bus_ehci0_clk.common,
    645	&bus_ehci1_clk.common,
    646	&bus_ehci2_clk.common,
    647	&bus_ehci3_clk.common,
    648	&bus_ohci0_clk.common,
    649	&bus_ohci1_clk.common,
    650	&bus_ohci2_clk.common,
    651	&bus_ohci3_clk.common,
    652	&bus_ve_clk.common,
    653	&bus_tcon0_clk.common,
    654	&bus_tcon1_clk.common,
    655	&bus_deinterlace_clk.common,
    656	&bus_csi_clk.common,
    657	&bus_tve_clk.common,
    658	&bus_hdmi_clk.common,
    659	&bus_de_clk.common,
    660	&bus_gpu_clk.common,
    661	&bus_msgbox_clk.common,
    662	&bus_spinlock_clk.common,
    663	&bus_codec_clk.common,
    664	&bus_spdif_clk.common,
    665	&bus_pio_clk.common,
    666	&bus_ths_clk.common,
    667	&bus_i2s0_clk.common,
    668	&bus_i2s1_clk.common,
    669	&bus_i2s2_clk.common,
    670	&bus_i2c0_clk.common,
    671	&bus_i2c1_clk.common,
    672	&bus_i2c2_clk.common,
    673	&bus_uart0_clk.common,
    674	&bus_uart1_clk.common,
    675	&bus_uart2_clk.common,
    676	&bus_uart3_clk.common,
    677	&bus_scr0_clk.common,
    678	&bus_scr1_clk.common,
    679	&bus_ephy_clk.common,
    680	&bus_dbg_clk.common,
    681	&ths_clk.common,
    682	&nand_clk.common,
    683	&mmc0_clk.common,
    684	&mmc1_clk.common,
    685	&mmc2_clk.common,
    686	&ts_clk.common,
    687	&ce_clk.common,
    688	&spi0_clk.common,
    689	&spi1_clk.common,
    690	&i2s0_clk.common,
    691	&i2s1_clk.common,
    692	&i2s2_clk.common,
    693	&spdif_clk.common,
    694	&usb_phy0_clk.common,
    695	&usb_phy1_clk.common,
    696	&usb_phy2_clk.common,
    697	&usb_phy3_clk.common,
    698	&usb_ohci0_clk.common,
    699	&usb_ohci1_clk.common,
    700	&usb_ohci2_clk.common,
    701	&usb_ohci3_clk.common,
    702	&dram_clk.common,
    703	&dram_ve_clk.common,
    704	&dram_csi_clk.common,
    705	&dram_deinterlace_clk.common,
    706	&dram_ts_clk.common,
    707	&de_clk.common,
    708	&tcon_clk.common,
    709	&tve_clk.common,
    710	&deinterlace_clk.common,
    711	&csi_misc_clk.common,
    712	&csi_sclk_clk.common,
    713	&csi_mclk_clk.common,
    714	&ve_clk.common,
    715	&ac_dig_clk.common,
    716	&avs_clk.common,
    717	&hdmi_clk.common,
    718	&hdmi_ddc_clk.common,
    719	&mbus_clk.common,
    720	&gpu_clk.common,
    721};
    722
    723static const struct clk_hw *clk_parent_pll_audio[] = {
    724	&pll_audio_base_clk.common.hw
    725};
    726
    727/* We hardcode the divider to 1 for now */
    728static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
    729			    clk_parent_pll_audio,
    730			    1, 1, CLK_SET_RATE_PARENT);
    731static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
    732			    clk_parent_pll_audio,
    733			    2, 1, CLK_SET_RATE_PARENT);
    734static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
    735			    clk_parent_pll_audio,
    736			    1, 1, CLK_SET_RATE_PARENT);
    737static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
    738			    clk_parent_pll_audio,
    739			    1, 2, CLK_SET_RATE_PARENT);
    740static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
    741			   &pll_periph0_clk.common.hw,
    742			   1, 2, 0);
    743
    744static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
    745	.hws	= {
    746		[CLK_PLL_CPUX]		= &pll_cpux_clk.common.hw,
    747		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
    748		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
    749		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
    750		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
    751		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
    752		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
    753		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
    754		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
    755		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
    756		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
    757		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
    758		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
    759		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
    760		[CLK_CPUX]		= &cpux_clk.common.hw,
    761		[CLK_AXI]		= &axi_clk.common.hw,
    762		[CLK_AHB1]		= &ahb1_clk.common.hw,
    763		[CLK_APB1]		= &apb1_clk.common.hw,
    764		[CLK_APB2]		= &apb2_clk.common.hw,
    765		[CLK_AHB2]		= &ahb2_clk.common.hw,
    766		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
    767		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
    768		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
    769		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
    770		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
    771		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
    772		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
    773		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
    774		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
    775		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
    776		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
    777		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
    778		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
    779		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
    780		[CLK_BUS_EHCI1]		= &bus_ehci1_clk.common.hw,
    781		[CLK_BUS_EHCI2]		= &bus_ehci2_clk.common.hw,
    782		[CLK_BUS_EHCI3]		= &bus_ehci3_clk.common.hw,
    783		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
    784		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
    785		[CLK_BUS_OHCI2]		= &bus_ohci2_clk.common.hw,
    786		[CLK_BUS_OHCI3]		= &bus_ohci3_clk.common.hw,
    787		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
    788		[CLK_BUS_TCON0]		= &bus_tcon0_clk.common.hw,
    789		[CLK_BUS_TCON1]		= &bus_tcon1_clk.common.hw,
    790		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
    791		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
    792		[CLK_BUS_TVE]		= &bus_tve_clk.common.hw,
    793		[CLK_BUS_HDMI]		= &bus_hdmi_clk.common.hw,
    794		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
    795		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
    796		[CLK_BUS_MSGBOX]	= &bus_msgbox_clk.common.hw,
    797		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
    798		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
    799		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
    800		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
    801		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
    802		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
    803		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
    804		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
    805		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
    806		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
    807		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
    808		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
    809		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
    810		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
    811		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
    812		[CLK_BUS_SCR0]		= &bus_scr0_clk.common.hw,
    813		[CLK_BUS_EPHY]		= &bus_ephy_clk.common.hw,
    814		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
    815		[CLK_THS]		= &ths_clk.common.hw,
    816		[CLK_NAND]		= &nand_clk.common.hw,
    817		[CLK_MMC0]		= &mmc0_clk.common.hw,
    818		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
    819		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
    820		[CLK_MMC1]		= &mmc1_clk.common.hw,
    821		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
    822		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
    823		[CLK_MMC2]		= &mmc2_clk.common.hw,
    824		[CLK_MMC2_SAMPLE]	= &mmc2_sample_clk.common.hw,
    825		[CLK_MMC2_OUTPUT]	= &mmc2_output_clk.common.hw,
    826		[CLK_TS]		= &ts_clk.common.hw,
    827		[CLK_CE]		= &ce_clk.common.hw,
    828		[CLK_SPI0]		= &spi0_clk.common.hw,
    829		[CLK_SPI1]		= &spi1_clk.common.hw,
    830		[CLK_I2S0]		= &i2s0_clk.common.hw,
    831		[CLK_I2S1]		= &i2s1_clk.common.hw,
    832		[CLK_I2S2]		= &i2s2_clk.common.hw,
    833		[CLK_SPDIF]		= &spdif_clk.common.hw,
    834		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
    835		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
    836		[CLK_USB_PHY2]		= &usb_phy2_clk.common.hw,
    837		[CLK_USB_PHY3]		= &usb_phy3_clk.common.hw,
    838		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
    839		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
    840		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,
    841		[CLK_USB_OHCI3]		= &usb_ohci3_clk.common.hw,
    842		[CLK_DRAM]		= &dram_clk.common.hw,
    843		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
    844		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
    845		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
    846		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
    847		[CLK_DE]		= &de_clk.common.hw,
    848		[CLK_TCON0]		= &tcon_clk.common.hw,
    849		[CLK_TVE]		= &tve_clk.common.hw,
    850		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
    851		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
    852		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
    853		[CLK_CSI_MCLK]		= &csi_mclk_clk.common.hw,
    854		[CLK_VE]		= &ve_clk.common.hw,
    855		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
    856		[CLK_AVS]		= &avs_clk.common.hw,
    857		[CLK_HDMI]		= &hdmi_clk.common.hw,
    858		[CLK_HDMI_DDC]		= &hdmi_ddc_clk.common.hw,
    859		[CLK_MBUS]		= &mbus_clk.common.hw,
    860		[CLK_GPU]		= &gpu_clk.common.hw,
    861	},
    862	.num	= CLK_NUMBER_H3,
    863};
    864
    865static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
    866	.hws	= {
    867		[CLK_PLL_CPUX]		= &pll_cpux_clk.common.hw,
    868		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
    869		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
    870		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
    871		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
    872		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
    873		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
    874		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
    875		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
    876		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
    877		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
    878		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
    879		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
    880		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
    881		[CLK_CPUX]		= &cpux_clk.common.hw,
    882		[CLK_AXI]		= &axi_clk.common.hw,
    883		[CLK_AHB1]		= &ahb1_clk.common.hw,
    884		[CLK_APB1]		= &apb1_clk.common.hw,
    885		[CLK_APB2]		= &apb2_clk.common.hw,
    886		[CLK_AHB2]		= &ahb2_clk.common.hw,
    887		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
    888		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
    889		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
    890		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
    891		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
    892		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
    893		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
    894		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
    895		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
    896		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
    897		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
    898		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
    899		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
    900		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
    901		[CLK_BUS_EHCI1]		= &bus_ehci1_clk.common.hw,
    902		[CLK_BUS_EHCI2]		= &bus_ehci2_clk.common.hw,
    903		[CLK_BUS_EHCI3]		= &bus_ehci3_clk.common.hw,
    904		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
    905		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
    906		[CLK_BUS_OHCI2]		= &bus_ohci2_clk.common.hw,
    907		[CLK_BUS_OHCI3]		= &bus_ohci3_clk.common.hw,
    908		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
    909		[CLK_BUS_TCON0]		= &bus_tcon0_clk.common.hw,
    910		[CLK_BUS_TCON1]		= &bus_tcon1_clk.common.hw,
    911		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
    912		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
    913		[CLK_BUS_TVE]		= &bus_tve_clk.common.hw,
    914		[CLK_BUS_HDMI]		= &bus_hdmi_clk.common.hw,
    915		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
    916		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
    917		[CLK_BUS_MSGBOX]	= &bus_msgbox_clk.common.hw,
    918		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
    919		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
    920		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
    921		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
    922		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
    923		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
    924		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
    925		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
    926		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
    927		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
    928		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
    929		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
    930		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
    931		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
    932		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
    933		[CLK_BUS_SCR0]		= &bus_scr0_clk.common.hw,
    934		[CLK_BUS_SCR1]		= &bus_scr1_clk.common.hw,
    935		[CLK_BUS_EPHY]		= &bus_ephy_clk.common.hw,
    936		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
    937		[CLK_THS]		= &ths_clk.common.hw,
    938		[CLK_NAND]		= &nand_clk.common.hw,
    939		[CLK_MMC0]		= &mmc0_clk.common.hw,
    940		[CLK_MMC1]		= &mmc1_clk.common.hw,
    941		[CLK_MMC2]		= &mmc2_clk.common.hw,
    942		[CLK_TS]		= &ts_clk.common.hw,
    943		[CLK_CE]		= &ce_clk.common.hw,
    944		[CLK_SPI0]		= &spi0_clk.common.hw,
    945		[CLK_SPI1]		= &spi1_clk.common.hw,
    946		[CLK_I2S0]		= &i2s0_clk.common.hw,
    947		[CLK_I2S1]		= &i2s1_clk.common.hw,
    948		[CLK_I2S2]		= &i2s2_clk.common.hw,
    949		[CLK_SPDIF]		= &spdif_clk.common.hw,
    950		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
    951		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
    952		[CLK_USB_PHY2]		= &usb_phy2_clk.common.hw,
    953		[CLK_USB_PHY3]		= &usb_phy3_clk.common.hw,
    954		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
    955		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
    956		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,
    957		[CLK_USB_OHCI3]		= &usb_ohci3_clk.common.hw,
    958		[CLK_DRAM]		= &dram_clk.common.hw,
    959		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
    960		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
    961		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
    962		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
    963		[CLK_DE]		= &de_clk.common.hw,
    964		[CLK_TCON0]		= &tcon_clk.common.hw,
    965		[CLK_TVE]		= &tve_clk.common.hw,
    966		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
    967		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
    968		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
    969		[CLK_CSI_MCLK]		= &csi_mclk_clk.common.hw,
    970		[CLK_VE]		= &ve_clk.common.hw,
    971		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
    972		[CLK_AVS]		= &avs_clk.common.hw,
    973		[CLK_HDMI]		= &hdmi_clk.common.hw,
    974		[CLK_HDMI_DDC]		= &hdmi_ddc_clk.common.hw,
    975		[CLK_MBUS]		= &mbus_clk.common.hw,
    976		[CLK_GPU]		= &gpu_clk.common.hw,
    977	},
    978	.num	= CLK_NUMBER_H5,
    979};
    980
    981static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
    982	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
    983	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
    984	[RST_USB_PHY2]		=  { 0x0cc, BIT(2) },
    985	[RST_USB_PHY3]		=  { 0x0cc, BIT(3) },
    986
    987	[RST_MBUS]		=  { 0x0fc, BIT(31) },
    988
    989	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
    990	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
    991	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
    992	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
    993	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
    994	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
    995	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
    996	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
    997	[RST_BUS_TS]		=  { 0x2c0, BIT(18) },
    998	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
    999	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
   1000	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
   1001	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
   1002	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
   1003	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },
   1004	[RST_BUS_EHCI2]		=  { 0x2c0, BIT(26) },
   1005	[RST_BUS_EHCI3]		=  { 0x2c0, BIT(27) },
   1006	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(28) },
   1007	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
   1008	[RST_BUS_OHCI2]		=  { 0x2c0, BIT(30) },
   1009	[RST_BUS_OHCI3]		=  { 0x2c0, BIT(31) },
   1010
   1011	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
   1012	[RST_BUS_TCON0]		=  { 0x2c4, BIT(3) },
   1013	[RST_BUS_TCON1]		=  { 0x2c4, BIT(4) },
   1014	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
   1015	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
   1016	[RST_BUS_TVE]		=  { 0x2c4, BIT(9) },
   1017	[RST_BUS_HDMI0]		=  { 0x2c4, BIT(10) },
   1018	[RST_BUS_HDMI1]		=  { 0x2c4, BIT(11) },
   1019	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
   1020	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
   1021	[RST_BUS_MSGBOX]	=  { 0x2c4, BIT(21) },
   1022	[RST_BUS_SPINLOCK]	=  { 0x2c4, BIT(22) },
   1023	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
   1024
   1025	[RST_BUS_EPHY]		=  { 0x2c8, BIT(2) },
   1026
   1027	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
   1028	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
   1029	[RST_BUS_THS]		=  { 0x2d0, BIT(8) },
   1030	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
   1031	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
   1032	[RST_BUS_I2S2]		=  { 0x2d0, BIT(14) },
   1033
   1034	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
   1035	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
   1036	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
   1037	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
   1038	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
   1039	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
   1040	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
   1041	[RST_BUS_SCR0]		=  { 0x2d8, BIT(20) },
   1042};
   1043
   1044static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
   1045	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
   1046	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
   1047	[RST_USB_PHY2]		=  { 0x0cc, BIT(2) },
   1048	[RST_USB_PHY3]		=  { 0x0cc, BIT(3) },
   1049
   1050	[RST_MBUS]		=  { 0x0fc, BIT(31) },
   1051
   1052	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
   1053	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
   1054	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
   1055	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
   1056	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
   1057	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
   1058	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
   1059	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
   1060	[RST_BUS_TS]		=  { 0x2c0, BIT(18) },
   1061	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
   1062	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
   1063	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
   1064	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
   1065	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
   1066	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },
   1067	[RST_BUS_EHCI2]		=  { 0x2c0, BIT(26) },
   1068	[RST_BUS_EHCI3]		=  { 0x2c0, BIT(27) },
   1069	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(28) },
   1070	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
   1071	[RST_BUS_OHCI2]		=  { 0x2c0, BIT(30) },
   1072	[RST_BUS_OHCI3]		=  { 0x2c0, BIT(31) },
   1073
   1074	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
   1075	[RST_BUS_TCON0]		=  { 0x2c4, BIT(3) },
   1076	[RST_BUS_TCON1]		=  { 0x2c4, BIT(4) },
   1077	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
   1078	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
   1079	[RST_BUS_TVE]		=  { 0x2c4, BIT(9) },
   1080	[RST_BUS_HDMI0]		=  { 0x2c4, BIT(10) },
   1081	[RST_BUS_HDMI1]		=  { 0x2c4, BIT(11) },
   1082	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
   1083	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
   1084	[RST_BUS_MSGBOX]	=  { 0x2c4, BIT(21) },
   1085	[RST_BUS_SPINLOCK]	=  { 0x2c4, BIT(22) },
   1086	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
   1087
   1088	[RST_BUS_EPHY]		=  { 0x2c8, BIT(2) },
   1089
   1090	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
   1091	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
   1092	[RST_BUS_THS]		=  { 0x2d0, BIT(8) },
   1093	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
   1094	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
   1095	[RST_BUS_I2S2]		=  { 0x2d0, BIT(14) },
   1096
   1097	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
   1098	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
   1099	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
   1100	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
   1101	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
   1102	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
   1103	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
   1104	[RST_BUS_SCR0]		=  { 0x2d8, BIT(20) },
   1105	[RST_BUS_SCR1]		=  { 0x2d8, BIT(20) },
   1106};
   1107
   1108static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
   1109	.ccu_clks	= sun8i_h3_ccu_clks,
   1110	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_ccu_clks),
   1111
   1112	.hw_clks	= &sun8i_h3_hw_clks,
   1113
   1114	.resets		= sun8i_h3_ccu_resets,
   1115	.num_resets	= ARRAY_SIZE(sun8i_h3_ccu_resets),
   1116};
   1117
   1118static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
   1119	.ccu_clks	= sun50i_h5_ccu_clks,
   1120	.num_ccu_clks	= ARRAY_SIZE(sun50i_h5_ccu_clks),
   1121
   1122	.hw_clks	= &sun50i_h5_hw_clks,
   1123
   1124	.resets		= sun50i_h5_ccu_resets,
   1125	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),
   1126};
   1127
   1128static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
   1129	.common	= &pll_cpux_clk.common,
   1130	/* copy from pll_cpux_clk */
   1131	.enable	= BIT(31),
   1132	.lock	= BIT(28),
   1133};
   1134
   1135static struct ccu_mux_nb sun8i_h3_cpu_nb = {
   1136	.common		= &cpux_clk.common,
   1137	.cm		= &cpux_clk.mux,
   1138	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
   1139	.bypass_index	= 1, /* index of 24 MHz oscillator */
   1140};
   1141
   1142static int sun8i_h3_ccu_probe(struct platform_device *pdev)
   1143{
   1144	const struct sunxi_ccu_desc *desc;
   1145	void __iomem *reg;
   1146	int ret;
   1147	u32 val;
   1148
   1149	desc = of_device_get_match_data(&pdev->dev);
   1150	if (!desc)
   1151		return -EINVAL;
   1152
   1153	reg = devm_platform_ioremap_resource(pdev, 0);
   1154	if (IS_ERR(reg))
   1155		return PTR_ERR(reg);
   1156
   1157	/* Force the PLL-Audio-1x divider to 1 */
   1158	val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
   1159	val &= ~GENMASK(19, 16);
   1160	writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
   1161
   1162	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
   1163	if (ret)
   1164		return ret;
   1165
   1166	/* Gate then ungate PLL CPU after any rate changes */
   1167	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
   1168
   1169	/* Reparent CPU during PLL CPU rate changes */
   1170	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
   1171				  &sun8i_h3_cpu_nb);
   1172
   1173	return 0;
   1174}
   1175
   1176static const struct of_device_id sun8i_h3_ccu_ids[] = {
   1177	{
   1178		.compatible = "allwinner,sun8i-h3-ccu",
   1179		.data = &sun8i_h3_ccu_desc,
   1180	},
   1181	{
   1182		.compatible = "allwinner,sun50i-h5-ccu",
   1183		.data = &sun50i_h5_ccu_desc,
   1184	},
   1185	{ }
   1186};
   1187
   1188static struct platform_driver sun8i_h3_ccu_driver = {
   1189	.probe	= sun8i_h3_ccu_probe,
   1190	.driver	= {
   1191		.name			= "sun8i-h3-ccu",
   1192		.suppress_bind_attrs	= true,
   1193		.of_match_table		= sun8i_h3_ccu_ids,
   1194	},
   1195};
   1196module_platform_driver(sun8i_h3_ccu_driver);
   1197
   1198MODULE_IMPORT_NS(SUNXI_CCU);
   1199MODULE_LICENSE("GPL");