cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

clk-816x.c (3446B)

      1/*
      2 * This program is free software; you can redistribute it and/or
      3 * modify it under the terms of the GNU General Public License as
      4 * published by the Free Software Foundation version 2.
      5 *
      6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
      7 * kind, whether express or implied; without even the implied warranty
      8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
      9 * GNU General Public License for more details.
     10 */
     11
     12#include <linux/kernel.h>
     13#include <linux/list.h>
     14#include <linux/clk-provider.h>
     15#include <linux/clk/ti.h>
     16#include <dt-bindings/clock/dm816.h>
     17
     18#include "clock.h"
     19
     20static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {
     21	{ DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
     22	{ 0 },
     23};
     24
     25static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {
     26	{ DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
     27	{ DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
     28	{ DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
     29	{ DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
     30	{ DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
     31	{ DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
     32	{ DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
     33	{ DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
     34	{ DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
     35	{ DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
     36	{ DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
     37	{ DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
     38	{ DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
     39	{ DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
     40	{ DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
     41	{ DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
     42	{ DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
     43	{ DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
     44	{ DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
     45	{ DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
     46	{ DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
     47	{ DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
     48	{ DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },
     49	{ DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
     50	{ DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
     51	{ DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
     52	{ DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
     53	{ DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
     54	{ DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
     55	{ 0 },
     56};
     57
     58const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {
     59	{ 0x48180500, dm816_default_clkctrl_regs },
     60	{ 0x48181400, dm816_alwon_clkctrl_regs },
     61	{ 0 },
     62};
     63
     64static struct ti_dt_clk dm816x_clks[] = {
     65	DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
     66	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
     67	DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
     68	DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
     69	{ .node_name = NULL },
     70};
     71
     72static const char *enable_init_clks[] = {
     73	"ddr_pll_clk1",
     74	"ddr_pll_clk2",
     75	"ddr_pll_clk3",
     76	"sysclk6_ck",
     77};
     78
     79int __init dm816x_dt_clk_init(void)
     80{
     81	ti_dt_clocks_register(dm816x_clks);
     82	omap2_clk_disable_autoidle_all();
     83	ti_clk_add_aliases();
     84	omap2_clk_enable_init_clocks(enable_init_clks,
     85				     ARRAY_SIZE(enable_init_clks));
     86
     87	return 0;
     88}