cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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scx200_hrt.c (2598B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2006 Jim Cromie
      4 *
      5 * This is a clocksource driver for the Geode SCx200's 1 or 27 MHz
      6 * high-resolution timer.  The Geode SC-1100 (at least) has a buggy
      7 * time stamp counter (TSC), which loses time unless 'idle=poll' is
      8 * given as a boot-arg. In its absence, the Generic Timekeeping code
      9 * will detect and de-rate the bad TSC, allowing this timer to take
     10 * over timekeeping duties.
     11 *
     12 * Based on work by John Stultz, and Ted Phelps (in a 2.6.12-rc6 patch)
     13 */
     14
     15#include <linux/clocksource.h>
     16#include <linux/init.h>
     17#include <linux/module.h>
     18#include <linux/ioport.h>
     19#include <linux/scx200.h>
     20
     21#define NAME "scx200_hrt"
     22
     23static int mhz27;
     24module_param(mhz27, int, 0);	/* load time only */
     25MODULE_PARM_DESC(mhz27, "count at 27.0 MHz (default is 1.0 MHz)");
     26
     27static int ppm;
     28module_param(ppm, int, 0);	/* load time only */
     29MODULE_PARM_DESC(ppm, "+-adjust to actual XO freq (ppm)");
     30
     31/* HiRes Timer configuration register address */
     32#define SCx200_TMCNFG_OFFSET (SCx200_TIMER_OFFSET + 5)
     33
     34/* and config settings */
     35#define HR_TMEN (1 << 0)	/* timer interrupt enable */
     36#define HR_TMCLKSEL (1 << 1)	/* 1|0 counts at 27|1 MHz */
     37#define HR_TM27MPD (1 << 2)	/* 1 turns off input clock (power-down) */
     38
     39/* The base timer frequency, * 27 if selected */
     40#define HRT_FREQ   1000000
     41
     42static u64 read_hrt(struct clocksource *cs)
     43{
     44	/* Read the timer value */
     45	return (u64) inl(scx200_cb_base + SCx200_TIMER_OFFSET);
     46}
     47
     48static struct clocksource cs_hrt = {
     49	.name		= "scx200_hrt",
     50	.rating		= 250,
     51	.read		= read_hrt,
     52	.mask		= CLOCKSOURCE_MASK(32),
     53	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
     54	/* mult, shift are set based on mhz27 flag */
     55};
     56
     57static int __init init_hrt_clocksource(void)
     58{
     59	u32 freq;
     60	/* Make sure scx200 has initialized the configuration block */
     61	if (!scx200_cb_present())
     62		return -ENODEV;
     63
     64	/* Reserve the timer's ISA io-region for ourselves */
     65	if (!request_region(scx200_cb_base + SCx200_TIMER_OFFSET,
     66			    SCx200_TIMER_SIZE,
     67			    "NatSemi SCx200 High-Resolution Timer")) {
     68		pr_warn("unable to lock timer region\n");
     69		return -ENODEV;
     70	}
     71
     72	/* write timer config */
     73	outb(HR_TMEN | (mhz27 ? HR_TMCLKSEL : 0),
     74	     scx200_cb_base + SCx200_TMCNFG_OFFSET);
     75
     76	freq = (HRT_FREQ + ppm);
     77	if (mhz27)
     78		freq *= 27;
     79
     80	pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm);
     81
     82	return clocksource_register_hz(&cs_hrt, freq);
     83}
     84
     85module_init(init_hrt_clocksource);
     86
     87MODULE_AUTHOR("Jim Cromie <jim.cromie@gmail.com>");
     88MODULE_DESCRIPTION("clocksource on SCx200 HiRes Timer");
     89MODULE_LICENSE("GPL");